Method for directly depositing palladium onto a non-activated surface of a gallium nitride semiconductor

Patent metadata

Field	Value
Publication number	US-10920322-B2
Application number	US-201716320123-A
Country	US
Kind code	B2
Filing date	Aug 21, 2017
Priority date	Aug 23, 2016
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

The present invention relates to a method for directly depositing palladium onto a non-activated surface of a gallium nitride semiconductor, the use of an acidic palladium plating bath (as defined below) for directly depositing metallic palladium or a palladium alloy onto a non-activated surface of a doped or non-doped gallium nitride semiconductor, and a palladium or palladium alloy coated, doped or non-doped gallium nitride semiconductor.

First claim

The invention claimed is:

1. Method for directly depositing palladium onto a non-activated surface of a gallium nitride semiconductor, comprising in this order the steps:
(i) providing a doped or non-doped gallium nitride semiconductor with a non-activated surface,
(ii) providing an aqueous, acidic palladium plating bath, comprising
(a) Pd 2+ ions,
(b) one or more than one reducing agent suitable to reduce Pd 2+ ions to metallic Pd 0 ,
(c) one or more than one compound selected from the group consisting of compounds of formulae (I) and (II)

wherein R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 , and R 8 are independently H, alkyl, aryl, hetero aryl, NH 2 , SO 3 H, or OH, and
R 9 is independently H, alkyl, aryl, or hetero aryl,

(iii) contacting the semiconductor with the plating bath such that metallic palladium or a palladium alloy is electrolessly deposited onto the non-activated surface of the semiconductor, the plating bath temperature being in the range of from 70° C. to 99° C.

2. Method according to claim 1 , wherein the surface of the semiconductor is not contacted with or does not comprise Sn 2+ ions prior to step (iii) or when step (iii) is carried out.

3. Method according to claim 1 comprising the additional step prior to step (iii)
cleaning the non-activated surface with a cleaning solution, the cleaning solution comprising one or more than one ingredient selected from the group consisting of acids, bases, oxidizing agents, halogen ions, and organic solvents.

4. Method according to claim 1 , wherein the pH of the acidic palladium plating bath is in the range of from 4.0 to 6.5.

5. Method according to claim 1 , wherein (c) is one or more than one compound of formula (I), wherein R 1 , R 2 , R 3 , and R 4 is H.

6. Method according to claim 1 , wherein the palladium plating bath additionally contains
(d) one or more than one complexing compound selected from amines.

7. Method according to claim 1 , wherein in step (iii) the semiconductor and the plating bath are in contact for 10 to 1200 seconds.

8. Method according to claim 1 , wherein the plating bath temperature in step (iii) is in the range of from 70° C. to 95° C.

9. Method according to claim 1 , wherein the deposited palladium and palladium alloy has a total layer thickness in the range of from 10 nm to 1000 nm.

10. Method according to claim 1 , wherein the metallic palladium or palladium alloy is selectively deposited onto the non-activated surface such that a palladium pattern or palladium alloy pattern is obtained on the surface of the semiconductor.

11. Method according to claim 1 comprising after step (iii) the additional step
(iv) depositing an additional metal layer or metal alloy layer onto the electrolessly deposited metallic palladium/palladium alloy obtained after step (iii).

12. Method according to claim 1 , wherein the surface of the semiconductor is not contacted with or does not comprise activation metal ions or activation metal atoms prior to step (iii) or when step (iii) is carried out.

13. Method according to claim 1 , wherein the pH of the acidic palladium plating bath is in the range of from 5.3 to 6.3.

14. Method according to claim 1 , wherein the compound of formula (I) is a saccharin salt.

15. Method according to claim 1 , wherein the non-activated surface of the semiconductor in step (i) by itself does not reduce Pd 2+ ions to metallic Pd 0 or mediates the reduction of Pd 2+ ions to metallic Pd 0 .

16. Method according to claim 1 comprising after step (iii) the additional step
(iv) depositing an additional metal layer or metal alloy layer onto the electrolessly deposited metallic palladium/palladium alloy obtained after step (iii) by electroless deposition.

Assignees

• Atotech Deutschland Gmbh

Inventors

• Walter Andreas

Classifications

• H10H20/825

  containing nitrogen, e.g. GaN · CPC title

• H10H20/01335

  the light-emitting regions comprising nitride materials · CPC title

• H10H20/8252

  characterised by the dopants · CPC title

• C23C18/1642

  semiconductor (semiconductor H10P14/48) · CPC title

• C23C18/44 Primary

  using reducing agents · CPC title