Photonic lock based high bandwidth photodetector

Patent metadata

Field	Value
Publication number	US-10916669-B2
Application number	US-201916502682-A
Country	US
Kind code	B2
Filing date	Jul 3, 2019
Priority date	Dec 10, 2012
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

The technique introduced herein decouples the traditional relationship between bandwidth and responsivity, thereby providing a more flexible and wider photodetector design space. In certain examples of the technique introduced here, a photodetector device includes a first mirror, a second mirror, and a light absorption region positioned between the first and second reflective mirrors. For example, the first mirror can be a low-reflectivity mirror, and the second mirror can be a high-reflectivity mirror. The light absorption region is positioned to absorb incident light that is passed through the first mirror and reflected between the first and second mirrors. The first mirror can be configured to exhibit a reflectivity that causes an amount of light energy that escapes from the first mirror, after the light being reflected back by the second mirror, to be zero or near zero.

First claim

What is claimed is:

1. A photodetector device comprising:
a first reflective region with a first reflectivity, wherein the first reflective region includes a first dielectric layer;
a waveguide laterally positioned adjacent to the first reflective region;
a cavity region including (1) a light absorption layer containing germanium, and (2) a buffer layer containing silicon; and
a second reflective region with a second reflectivity that is larger than the first reflectivity, wherein the second reflective region includes (1) a reflective layer including a coating of metal, and (2) a second dielectric layer positioned between the reflective layer and the cavity region,
wherein the cavity region is positioned between the first and second dielectric layers.

2. The device of claim 1 , wherein the second dielectric layer includes an oxide layer.

3. The device of claim 1 , wherein the first dielectric layer comprises oxide, and wherein a thickness of the first dielectric layer is larger than 100 nm.

4. The device of claim 1 , wherein the light absorption layer has a thickness ranging from 100 nm to 1.5 μm.

5. The device of claim 4 , wherein a length of the absorption layer is shorter than 1 μm.

6. The device of claim 1 , further including a layer of silicon, wherein the first dielectric layer is between the layer of silicon and the buffer layer.

7. The device of claim 6 , further including an anti-reflection coating layer, wherein the layer of silicon is between the anti-reflection coating layer and the first dielectric layer.

8. The device of claim 1 , wherein the first reflective region is selected from a group comprising: a distributed Bragg reflector (DBR), a metallic reflector, a dielectric layer, a dielectric-metal layer, a loop mirror, a corner mirror, and a reflection trench.

9. The device of claim 1 , wherein a structure of the cavity region comprises one or more of: a p-n doping profile, a p-i-n doping profile, a p-i-p-i-n doping profile, or a n-i-n-i-p doping profile.

10. The device of claim 1 , wherein the cavity region, or the first reflective region, or the second reflective region comprises a group III-V compound, silicon, germanium, an organic material, or a combination thereof.

11. The device of claim 1 , further comprising:
a waveguide coupled to the first reflective region.

12. The device of claim 1 , wherein a thickness of the buffer layer is not more than 1.5 μm.

13. The device of claim 1 , further comprising:
a substrate containing silicon.

14. The device of claim 1 , wherein a bandgap of a material of the waveguide is larger than a band gap of a material of the absorption layer, and wherein the waveguide is laterally aligned with the first reflective region in a horizontal plane.

15. The device of claim 1 , wherein a length of the absorption layer is shorter than 1 μm.

16. The device of claim 1 , wherein the first reflective region and the second reflective region are formed on a same planar surface.

17. The device of claim 1 , further comprising a substrate comprising a top surface, wherein the first reflective region and the second reflective region are coplanarly formed on the same top surface.

18. The device of claim 1 , wherein the first dielectric layer comprises oxide.

19. The device of claim 1 , wherein a thickness of the first dielectric layer is larger than 100 nm.

20. The device of claim 1 , wherein a thickness of the second dielectric layer is no more than 5 μm.

Assignees

• Artilux Inc

Inventors

• Chen Shu-Lu
• Na Yun-Chung

Classifications

• H10F71/00

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

• H10F30/22

  the devices having only one potential barrier, e.g. photodiodes · CPC title

• H10F30/225

  the potential barrier working in avalanche mode, e.g. avalanche photodiodes · CPC title

• H10F77/413 Primary

  directly associated or integrated with the devices, e.g. back reflectors (directly associated or integrated with photovoltaic cells H10F77/42) · CPC title

• H10F30/223 Primary

  the potential barrier being a PIN barrier · CPC title