Display apparatus including conductive pattern in substrate and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10916619-B2
Application number	US-202016783733-A
Country	US
Kind code	B2
Filing date	Feb 6, 2020
Priority date	Feb 28, 2017
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A display apparatus includes a display region and a peripheral region adjacent to the display region. The display apparatus further includes a first flexible substrate (FFS), a driving circuit (DC), a conductive pattern (CP), a conductive line, a light-emitting device, and a support substrate. The FFS includes a first surface and a second surface opposite the first surface. The second surface includes, in the peripheral region, a cavity extending into the FFS. The DC is on the first surface and includes at least one transistor. The CP is in the cavity and is partially exposed by the cavity. The conductive line electrically connects the CP to the DC. The light-emitting device is in the display region and is electrically connected to the DC. The support substrate is on the second surface. In a view normal to the second surface, the support substrate is spaced apart from the CP.

First claim

What is claimed is:

1. A method of manufacturing a display apparatus comprising a display region and a peripheral region, the method comprising:
forming a second flexible substrate on a carrier substrate;
forming a conductive pattern on the second flexible substrate in the peripheral region;
forming a first flexible substrate on the second flexible substrate;
forming, on a first surface of the first flexible substrate, a driving circuit comprising at least one transistor, and a conductive line electrically connecting the conductive pattern to the driving circuit;
forming, in the display region, a light-emitting device electrically connected to the driving circuit;
exposing the conductive pattern by removing the carrier substrate and at least a portion of the second flexible substrate; and
forming a support substrate on a second surface of the first flexible substrate such that the conductive pattern is exposed, the second surface being opposite the first surface.

2. The method of claim 1 , further comprising:
forming, after forming the first flexible substrate, an insulation structure to cover at least the conductive pattern; and
forming, in the insulation structure, a contact hole to electrically connect the conductive pattern to the conductive line.

3. The method of claim 2 , wherein:
forming the insulation structure comprises sequentially forming a buffer layer, a gate insulation layer, and an interlayer insulation layer on the first flexible substrate; and
the at least one transistor comprises an active layer on the buffer layer and a gate electrode on the gate insulation layer, the active layer being insulated from the active layer via the gate insulation layer.

4. The method of claim 1 , further comprising:
forming, after forming the conductive pattern, an adhesion layer covering at least the conductive pattern.

5. The method of claim 1 , wherein materials of the first flexible substrate and the second flexible substrate are equivalent.

6. The method of claim 1 , wherein forming the first flexible substrate comprises forming a portion of the first flexible substrate on an upper surface of the conductive pattern with a thickness of 0 nm to about 150 nm.

7. The method of claim 1 , wherein exposing the conductive pattern comprises:
radiating a laser towards the carrier substrate and the second flexible substrate; and
simultaneously removing the carrier substrate and at least a portion of the second flexible substrate.

8. The method of claim 7 , wherein the second flexible substrate is formed with a thickness of less than or equal to about 0.1 μm, but greater than 0 μm.

9. The method of claim 7 , wherein, after simultaneous removal of the carrier substrate and the at least a portion of the second flexible substrate, the conductive pattern is exposed by removing a portion of the second flexible substrate remaining on a lower surface of the conductive pattern.

10. The method of claim 1 , further comprising:
performing, after forming the conductive pattern, a hydrophobic processing on at least an upper surface of the conductive pattern.

Assignees

• Samsung Display Co Ltd

Inventors

• Seo Kiseong
• Ryu Jekil
• Choe Wonkyu
• Choi Jungho
• Kim Mugyeom
• Jeong Changyong

Classifications

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D86/0214

  using temporary substrates · CPC title