Thin-film transistor and method of forming an electrode of a thin-film transistor

Patent metadata

Field	Value
Publication number	US-10916569-B2
Application number	US-201815895172-A
Country	US
Kind code	B2
Filing date	Feb 13, 2018
Priority date	Jun 6, 2013
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

In various embodiments, electronic devices such as touch-panel displays incorporate interconnects featuring a conductor layer and, disposed above the conductor layer, a capping layer comprising an alloy of Cu and one or more refractory metal elements selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni.

First claim

What is claimed is:

1. A thin-film transistor comprising:
a substrate comprising at least one of silicon or glass; and
an electrode comprising:
(i) disposed on the substrate, a barrier layer (i) comprising an alloy of Cu and one or more refractory metal elements selected from the list consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni, and (ii) comprising a plurality of crystalline grains separated by grain boundaries, and
(ii) disposed on the barrier layer, a conductor layer comprising at least one of Cu, Ag, Al, or Au,

wherein at least one of the grain boundaries comprises a particulate therein, the particulate comprising at least one of (i) an agglomeration of at least one of the refractory metal elements or (ii) a reaction product of silicon and at least one of the refractory metal elements.

2. The thin-film transistor of claim 1 , wherein the barrier layer comprises an alloy of Ta and Cu.

3. The thin-film transistor of claim 1 , wherein the barrier layer comprises an alloy of Nb and Cu.

4. The thin-film transistor of claim 1 , wherein the barrier layer comprises an alloy of Ta, Zr, and Cu.

5. The thin-film transistor of claim 1 , wherein the barrier layer comprises an alloy of Cu, Ta, and Ti.

6. The thin-film transistor of claim 1 , wherein (i) the conductor layer comprises Cu, and (ii) the substrate is substantially free of Cu diffusion from the conductor layer.

7. The thin-film transistor of claim 1 , wherein the substrate comprises glass.

8. The thin-film transistor of claim 1 , wherein the substrate comprises silicon.

9. The thin-film transistor of claim 8 , wherein the substrate comprises amorphous silicon.

10. A method of forming an electrode of a thin-film transistor, the method comprising:
providing a substrate comprising at least one of silicon or glass;
depositing over the substrate a barrier layer (i) comprising an alloy of Cu and one or more refractory metal elements selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni, and (ii) comprising a plurality of crystalline grains separated by grain boundaries;
depositing over the barrier layer a conductor layer comprising at least one of Cu, Ag, Al, or Au;
forming a mask layer over the barrier layer;
patterning the mask layer to reveal a portion of the conductor layer, a remaining portion of the mask layer at least partially defining a shape of the electrode;
thereafter, applying an etchant to remove portions of the conductor layer and the barrier layer not masked by the patterned mask layer, thereby forming a sidewall of the electrode comprising (i) an exposed portion of the barrier layer, (ii) an exposed portion of the conductor layer, and (iii) an interface between the exposed portion of the barrier layer and the exposed portion of the conductor layer; and
annealing the electrode at a temperature sufficient to form a particulate within at least one of the grain boundaries, the particulate comprising at least one of (i) an agglomeration of at least one of the refractory metal elements or (ii) a reaction product of silicon and at least one of the refractory metal elements.

11. The method of claim 10 , wherein, after the etchant is applied, the sidewall of the electrode is substantially free of discontinuities notwithstanding the interface.

12. The method of claim 10 , wherein the etchant comprises a mixture of phosphoric acid, acetic acid, nitric acid, and water.

13. The method of claim 10 , wherein the barrier layer comprises an alloy of Ta and Cu.

14. The method of claim 10 , wherein the barrier layer comprises an alloy of Nb and Cu.

15. The method of claim 10 , wherein the barrier layer comprises an alloy of Ta, Zr, and Cu.

16. The method of claim 10 , wherein the barrier layer comprises an alloy of Cu, Ta, and Ti.

17. The method of claim 10 , wherein the substrate comprises glass.

18. The method of claim 10 , wherein the substrate comprises silicon.

19. The method of claim 18 , wherein the substrate comprises amorphous silicon.

20. The method of claim 10 , further comprising removing the remaining portion of the patterned mask layer.

Assignees

• Sun Shuwei
• Dary Francois Charles
• Abouaf Marc
• Hogan Patrick
• Zhang Qi
• Starck H C Inc

Inventors

• Sun Shuwei
• Dary Francois-Charles
• Abouaf Marc
• Hogan Patrick
• Zhang Qi

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title

• H10D30/6746

  Amorphous silicon · CPC title