Semiconductor device

Patent metadata

Field	Value
Publication number	US-10916543-B2
Application number	US-201916726322-A
Country	US
Kind code	B2
Filing date	Dec 24, 2019
Priority date	Apr 7, 2017
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
first to fourth active regions extending in a first direction on a substrate and spaced apart from in a second direction intersecting the first direction,
wherein the first and second active regions overlap entirely with each other in the second direction, wherein the third and fourth active regions overlap entirely with each other in the second direction,
wherein the second and third active regions overlap partially with each other in the second direction, and
wherein the second active region is disposed between the first and third active regions and the third active region is disposed between the second and fourth active regions;
fifth to eighth active regions extending in the first direction on the substrate and spaced apart from in the second direction intersecting the first direction and disposed with spacing apart from the first to fourth active regions in the first direction,
wherein the fifth and sixth active regions overlap entirely with each other in the second direction, wherein the seventh and eighth active regions overlap entirely with each other in the second direction;
a device isolation film configured to define the first to eighth active regions; and
a gate structure formed on the first to fourth active regions and extending in the second direction,
wherein the fifth active region is positioned under the first active region in the first direction, and the sixth active region is positioned under the second active region in the first direction,
wherein the seventh active region is positioned above the third active region in the first direction, and the eighth active region is positioned above the fourth active region in the first direction,
wherein the fifth active region and the sixth active region are disposed to be only partially overlapped with the third active region and the fourth active region in the second direction,
wherein the seventh active region and the eighth active region are disposed to be only partially overlapped with the first active region and the second active region in the second direction, and
wherein the second and third active regions are disposed in misalignment with each other.

2. The semiconductor device of claim 1 , wherein a lower end portion of the second active region in the first direction is disposed higher than a lower end portion of the third active region.

3. The semiconductor device of claim 1 , wherein an upper end portion of the second active region is disposed higher than an upper end portion of the third active region.

4. The semiconductor device of claim 1 , wherein the first to fourth active regions respectively include first to fourth source contacts and first to fourth drain contacts respectively.

5. The semiconductor device of claim 4 , wherein the first source contact and the first drain contact are disposed in a downward direction along the first direction in the first active region, and the second source contact and the second drain contact are formed in the downward direction along the first direction in the second active region.

6. The semiconductor device of claim 4 , wherein the third source contact and the third drain contact are disposed in an upward direction along the first direction in the third active region, and the fourth source contact and the fourth drain contact are disposed in the upward direction along the first direction in the fourth active region.

7. The semiconductor device of claim 4 , wherein the second source contact and the second drain contact of the second active region are disposed in misalignment with the third source contact and the third drain contact of the third active region.

8. The semiconductor device of claim 1 , wherein the device isolation film comprises a first device isolation film positioned between the first active region and the second active region, a second device isolation film positioned between the second active region and the third active region, and a third device isolation film positioned between the third active region and the fourth active region.

9. The semiconductor device of claim 8 , wherein a width of the first device isolation film in the second direction is less than a width of the second device isolation film in the second direction.

10. The semiconductor device of claim 1 , wherein the fifth and eighth active regions do not overlap with each other in the second direction.

11. The semiconductor device of claim 1 , wherein the sixth and seventh active regions do not overlap with each other in the second direction.

12. A semiconductor device, comprising:
first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction,
wherein the first and second active regions are arranged so as to be overlapped entirely with each other in the second direction;
third and fourth active regions extending in the first direction on the substrate and spaced apart from the first active region in the second direction,
wherein the third and fourth active regions are arranged so as to be overlapped entirely with each other in the second direction,
wherein the second active region is positioned between the first and third active regions in the second direction,
wherein the third active region is positioned between the second and fourth active regions in the second direction,
wherein the second and third active regions are arranged so as to be only partially overlapped in the second direction, and
wherein the second and third active regions are disposed in misalignment with each other;
a device isolation film configured to define the first to fourth active regions;
a gate structure formed on the first to fourth active regions and extending in the second direction,
wherein the gate structure comprises a first portion extending on the first and second acfive regions in the second direction,
a second portion extending on the third and fourth acfive regions in the second direction;
first and second drain regions formed in a lower direction based on the gate structure; and
third and fourth drain regions formed in an upper direction based on the gate structure,
wherein the first portion comprises a first projecting portion which projects in a direction of the first drain region and the second drain region, the first projecting portion having a shape of surrounding the first drain region and the second drain region,
wherein the second portion comprises a second projecting portion which projects in a direction of the third drain region and the fourth drain region, the second projecting portion having a shape of surrounding the third drain region and the fourth drain region,
wherein the first portion and the second portion are disposed in misalignment with each other in the first direction, and
wherein a projecting direction of the first projecting portion and a projecting direction of the second projecting portion are opposite each other.

13. The semiconductor device of claim 12 , further comprising a third portion connecting the first and second portions and being formed in the second and third active regions.

14. The semiconductor device of claim 12 , wherein the first drain region and the second drain region are spaced apart from each other in the second direction, and wherein a portion of the first projecting portion is between the first drain region and the second drain region.

15. The semiconductor device of claim 12 , wherein the first projecting portion is disposed on the device isolation film surrounding the first and second acti

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Seung Uk
• Kim Taek Yong
• Yamada Satoru
• Lim Jun Hee
• Hur Ki Jae

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title