Pixel circuit and display panel
US-2024428730-A1 · Dec 26, 2024 · US
US10916189B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10916189-B2 |
| Application number | US-201916544032-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 19, 2019 |
| Priority date | Jun 22, 2018 |
| Publication date | Feb 9, 2021 |
| Grant date | Feb 9, 2021 |
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A scan driver comprises a level shifter configured to output varied clock signals that have different frequencies for at least two consecutive periods; and a shift register operating based on the varied clock signals output from the level shifter and outputting scan signals.
Opening claim text (preview).
What is claimed is: 1. A scan driver comprising: a level shifter configured to output a plurality of varied clock signals that have different frequencies for at least two consecutive periods; and a shift register configured to operate based on the plurality of clock signals and outputting scan signals, wherein each clock signal is frequency modulated by fixing pulse width of each clock signal and varying lengths of the at least two consecutive periods. 2. The scan driver of claim 1 , wherein at least one of the plurality of clock signals has a pulse width different from a pulse width of at least one of other clock signals. 3. The scan driver of claim 1 , wherein the level shifter assigns at least two clock signals as one pair during a same period and varies a pulse width of the plurality of clock signals. 4. The scan driver of claim 3 , wherein, when the pulse width of one of the clock signals increases, the level shifter outputs the clock signals with varied pulse widths by decreasing the pulse width of the other clock signal. 5. The scan driver of claim 1 , wherein, when the length of one period of the at least two consecutive periods increases, the level shifter decreases the length of the other period. 6. The scan driver of claim 1 , wherein the shift register outputs scan signals dispersed in multiple frequency bands. 7. A display device comprising: a scan driver configured to output scan signals dispersed in multiple frequency bands; a data driver configured to output data signals; a timing controller configured to control the scan driver and the data driver; and a display panel configured to display an image based on the scan signals and the data signals, wherein the scan driver comprises: a level shifter configured to output a plurality of clock signals for at least two consecutive periods; and a shift register configured to operate based on the plurality of clock signals and output scan signals, wherein each clock signal is frequency modulated by fixing pulse width of each clock signal and varying lengths of the at least two consecutive periods. 8. The display device of claim 7 , further comprising a clock signal controller configured to generate a frequency modulation value based on at least one of image information displayed on the display panel and positional information of the display panel and to provide a clock signal control signal for causing frequency dispersion with respect to the scan signals based on the frequency modulation value to the level shifter. 9. The display device of claim 8 , wherein the clock signal controller controls frequency modulation ranges of scan signals applied to a center area of the display panel, an upper area of the display panel and a lower area of the display panel such that the frequency modulation ranges become different based on the at least one of image information displayed on the display panel and the positional information of the display panel. 10. The scan driver of claim 7 , wherein the level shifter assigns at least two clock signals as one pair during a same period and varies a pulse width of the plurality of clock signals. 11. The scan driver of claim 10 , wherein, when the pulse width of one of the clock signals increases, the level shifter outputs the clock signals with varied pulse widths by decreasing the pulse width of the other clock signal. 12. The display device of claim 7 , wherein the level shifter varies the periods of the clock signals in such a manner that, when the length of one period of the at least two consecutive periods increases, the length of the other period decreases. 13. The display device of claim 8 , wherein the clock signal controller generates the clock signal control signal with an on clock and an off clock respectively having a logic high and a logic low, and logic high durations of the on clock and the off clock are do overlap each other. 14. The display device of claim 11 , wherein the level shifter outputs varied clock signals that have different frequencies in response to edges of the on clock and the off clock. 15. The display device of claim 14 , wherein the clock signals become a logic high in response to a rising edge of the on clock and a logic low in response to a falling edge of the off clock, become a logic high in response to a falling edge of the on clock and a logic low in response to the falling edge of the off clock, become a logic high occurring in response to the falling edge of the on clock and a logic low in response to a rising edge of the off clock, or become a logic high in response to the rising edge of the on clock and a logic low in response to the rising edge of the off clock. 16. The display device of claim 13 , wherein durations of the logic high and the logic low constituting the on clock and the off clock are variable. 17. A display device comprising: a scan driver configured to output scan signals that have at least two different frequency bands; a data driver configured to output data signals; a timing controller configured to control the scan driver and the data driver; a display panel configured to display an image on the basis of the scan signals and the data signals; and a clock signal controller configured to generate a frequency modulation value based on at least one of image information displayed on the display panel and positional information of the display panel and to provide a clock signal control signal for causing frequency dispersion with respect to the scan signals based on the frequency modulation value to the scan driver, wherein the clock signal controller varies a length of a period of the scan signals.
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