Method and device for the synchronization of processes on at least two processors

Patent metadata

Field	Value
Publication number	US-10915375-B2
Application number	US-201815999196-A
Country	US
Kind code	B2
Filing date	Aug 16, 2018
Priority date	Aug 18, 2017
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A method and device for the synchronization of processes, a first signal being sent by a clock-giving processor, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge, a temporal distance between at least one of the first edges and at least one of the second edges being determined as a function of a state of a counter in the clock-giving processor. A method for the synchronization of processes, a first signal being received by a clock-receiving processor, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge, a state of a counter in the clock-receiving processor being determined as a function of a temporal distance between at least one of the first edges and at least one of the second edges.

First claim

What is claimed is:

1. A method for synchronizing processes, the method comprising:
sending, via a clock-giving processor, a first signal to a clock-receiving processor, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge, wherein a temporal distance, between one of the first edges in the first signal and one of the second edges which immediately follows the one of the first edges in the first signal, is determined by the clock-giving processor as a function of a state of a counter in the clock-giving processor; and
receiving, by the clock-giving processor, a second signal sent from the clock-receiving processor in response to the first signal, the second signal confirming a successful synchronization of the clock-receiving processor with the counter of the clock-giving processor.

2. The method of claim 1 , wherein the first signal is sent by the clock-giving processor with periodically repeating first edges.

3. The method of claim 2 , wherein on the clock-giving processor, a process is started after the receipt of the second signal and synchronous with the periodically repeating first edges.

4. The method of claim 1 , wherein the second signal and the first signal are sent via the same signal line, in a time-division multiplexing method.

5. The method of claim 1 , wherein the second signal and the first signal are sent on different signal lines.

6. The method as recited in claim 1 , wherein the temporal distance determined by the clock-giving processor encodes a value of the counter in the clock-giving processor.

7. The method as recited in claim 1 , wherein the counter in the clock-giving processor is configured to increment from 0 to N−1 and then to start again at 0, wherein N−1 is a highest counter state of the counter in the clock-giving parameter.

8. A method for synchronizing processes, the method comprising:
receiving, via a clock-receiving processor from a clock-sending processor, a first signal, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge; and
determining a state of a counter in the clock-receiving processor as a function of a temporal distance between one of the first edges in the first signal and one of the second edges which immediately follows the one of the first edges in the first signal;
wherein the temporal distance encodes a value of a counter in the clock-sending processor; and wherein the method further comprises:
setting a value of the counter in the clock-receiving processor to the encoded value of the counter in the clock-sending processor to synchronize the counter in the clock-receiving processor with the counter in the clock-sending processor.

9. The method of claim 8 , wherein the first signal is received by the clock-receiving processor with periodically repeating first edges.

10. The method of claim 9 , wherein the clock-receiving processor sends a second signal that confirms a successful synchronization of the counter of the clock-receiving processor.

11. The method of claim 10 , wherein the second signal and the first signal are received via the same signal line, in a time-division multiplexing method.

12. The method of claim 10 , wherein the second signal and the first signal are received on different signal lines.

13. The method of claim 10 , wherein on the clock-receiving processor, a process is started, after the sending of the second signal, and synchronous with the periodically repeating first edges.

14. A device for synchronizing processes, comprising:
a clock-giving processor configured to:
send, via the clock-giving processor, a first signal to a clock-receiving processor, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge, wherein a temporal distance, between one of the first edges in the first signal and one of the second edges which immediately follows the one of the first edges in the first signal, is determined by the clock-giving processor as a function of a state of a counter in the clock-giving processor; and
receive, by the clock-giving processor, a second signal sent from the clock-receiving processor in response to the first signal, the second signal confirming a successful synchronization of the clock-receiving processor with the counter of the clock-giving processor.

15. The device as recited in claim 14 , wherein the temporal distance determined by the clock-giving processor encodes a value of the counter in the clock-giving processor.

16. The device as recited in claim 14 , wherein the counter in the clock-giving processor is configured to increment from 0 to N−1 and then to start again at 0, wherein N−1 is a highest counter state of the counter in the clock-giving parameter.

17. A device for synchronizing processes, comprising:
a clock-receiving processor configured to:
receive, via the clock-receiving processor from a clock-sending processor, a first signal, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge; and
determine a state of a counter in the clock-receiving processor as a function of a temporal distance between one of the first edges in the first signal and one of the second edges which immediately follows the one of the first edges in the first signal;
wherein the temporal distance encodes a value of a counter in the clock-sending processor; and wherein the clock-receiving processor is further configured to:
set a value of the counter in the clock-receiving processor to the encoded value of the counter in the clock-sending processor to synchronize the counter in the clock-receiving processor with the counter in the clock-sending processor.

18. A non-transitory computer readable medium on which is stored a computer program including program code for synchronizing processes, the program code, when executed by a processor, causing the processor to perform the following:
sending, via a clock-giving processor, a first signal to a clock-receiving processor, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge, wherein a temporal distance, between one of the first edges in the first signal and one of the second edges which immediately follows the one of the first edges in the first signal, is determined by the clock-giving processor as a function of a state of a counter in the clock-giving processor; and
receiving, by the clock-giving processor, a second signal sent from the clock-receiving processor in response to the first signal, the second signal confirming a successful synchronization of the clock-receiving processor with the counter of the clock-giving processor.

Assignees

• Bosch Gmbh Robert

Inventors

• Gebauer Thomas
• Mueller Christoph
• Miranda Cristina Murillo

Classifications

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• H04L7/0091

  Transmitter details · CPC title

• H04L7/02

  Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)} · CPC title

• H04L25/49

  using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title