Two dimensional masked shift instruction

Patent metadata

Field	Value
Publication number	US-10915319-B2
Application number	US-201715595600-A
Country	US
Kind code	B2
Filing date	May 15, 2017
Priority date	May 15, 2017
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.

First claim

The invention claimed is:

1. An image processor, comprising:
an array of processing elements; and
a two-dimensional shift-register array having circuitry configured to support execution of a masked shift instruction, the masked shift instruction having mask information, wherein the mask information specifies which array locations in the two-dimensional shift-register array are to be written to with data being shifted in the two-dimensional shift-register array, the two-dimensional shift-register array comprising masking logic circuitry configured to write the data being shifted into respective array locations in accordance with the mask information,
wherein each processing element of the array of processing elements is configured to receive the masked shift instruction and to decode the masked shift instruction by using the mask information and a respective location of the processing element within the array of processing elements to determine whether or not the processing element should enable writing, to a shift-register dedicated to the processing element, data shifted by a different respective processing element in the array of processing elements.

2. The image processor of claim 1 , wherein the masking logic circuitry is distributed into array locations of the two-dimensional shift-register array.

3. The image processor of claim 1 , wherein the mask information comprises a code that specifies a write pattern over a subset of the two-dimensional shift-register array.

4. The image processor of claim 1 , wherein the mask information specifies which rows of the two-dimensional shift-register array are to be written to with data being shifted.

5. The image processor of claim 1 , wherein the mask information specifies which columns of the two-dimensional shift-register array are to be written to with data being shifted.

6. The image processor of claim 1 , wherein the mask information specifies that every other pair of columns of the two-dimensional shift-register array is to be written to with data being shifted.

7. The image processor of claim 1 , wherein the mask information specifies that every other quartet of columns of the two-dimensional shift-register array is to be written to with data being shifted.

8. One or more non-transitory machine-readable storage media encoded with program code having a masked shift instruction, wherein executing the program code by an image processor comprising an array of processing elements and a two-dimensional shift-register array causes the image processor to perform operations comprising:
receiving, by the image processor, the masked shift instruction having mask information, wherein the mask information specifies which of the array locations are to be written to with data being shifted in the two-dimensional shift-register array;
providing the masked shift instruction to each processing element of the array of processing elements;
decoding, by each processing element of the array of processing elements, the masked shift instruction using the mask information and a respective location of the processing element within the array of processing elements to determine whether or not the processing element should enable writing, to a shift-register dedicated to the processing element, data shifted by a different respective processing element in the array of processing elements;
receiving, by each processing element of the array of processing elements, data shifted by a different respective processing element in the array of processing elements; and
writing, by each processing element of one or more processing elements, the data shifted by the different respective processing element based on decoding the masked shift instruction.

9. The one or more machine-readable storage media of claim 8 , wherein the two-dimensional shift-register array comprises a halo region and wherein the operations further comprise performing a halo extension emulation method.

10. The one or more machine-readable storage media of claim 8 , wherein the operations further comprise performing a compaction method that reduces an image size.

11. The one or more machine-readable storage media of claim 8 , wherein the operations further comprise performing an expansion method that enlarges an image size.

12. The one or more machine-readable storage media of claim 8 , wherein the operations further comprise performing a broadcast method that repeats a same value across multiple locations of the two-dimensional shift-register array.

13. The one or more machine-readable storage media of claim 8 , wherein the operations further comprise performing a butterfly operation.

14. A computing system, comprising:
a plurality of general purpose processing cores;
a main memory;
a main memory controller coupled between the general purpose processing cores and the main memory;
an image processor, the image processor comprising
an array of processing elements; and
a two-dimensional shift-register array having circuitry configured to support execution of a masked shift instruction, the masked shift instruction having mask information, wherein the mask information specifies which array locations in the two-dimensional shift-register array are to be written to with data being shifted in the two-dimensional shift-register array, the two-dimensional shift-register array comprising masking logic circuitry configured to write the data being shifted into respective array locations in accordance with the mask information,
wherein each processing element of the array of processing elements is configured to receive the masked shift instruction and to decode the masked shift instruction by using the mask information and a respective location of the processing element within the array of processing elements to determine whether or not the processing element should enable writing, to a shift-register dedicated to the processing element, data shifted by a different respective processing element in the array of processing elements.

15. The computing system of claim 14 , wherein the masking logic circuitry is distributed into array locations of the two-dimensional shift-register array.

16. The computing system of claim 14 , wherein the mask information comprises a code that specifies a write pattern over a subset of the two-dimensional shift-register array.

17. The computing system of claim 14 , wherein the mask information specifies which rows of the two-dimensional shift-register array are to be written to with data being shifted.

18. The computing system of claim 14 , wherein the mask information specifies which columns of the two-dimensional shift-register array are to be written to with data being shifted.

19. The computing system of claim 14 , wherein the mask information specifies that every other pair of columns of the two-dimensional shift-register array is to be written to with data being shifted.

20. The computing system of claim 19 , wherein the mask information specifies that every other quartet of columns of the two-dimensional shift-register array is to be written to with data being shifted.

21. A method performed by an image processor comprising an array of processing elements and a two-dimensional shift-register array, the method comprising:
receiving, by the image processor, a masked shift instruction having mask information, wherein the mask information specifies which array locations in the two-dimensional shift-register array are to be written to with data being shifted in the two-dimensional shift-regist

Assignees

• Google Llc

Inventors

• Meixner Albert

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T5/90

  Dynamic range modification of images or parts thereof · CPC title

• G06F9/30134

  Register stacks; shift registers · CPC title

• G11C19/38

  two-dimensional [2D], e.g. horizontal and vertical shift registers · CPC title

• H04N19/44

  Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder · CPC title