Bi-directional negotiation for dynamic data chunking

Patent metadata

Field	Value
Publication number	US-10915258-B2
Application number	US-201715857158-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

Systems and techniques for bi-directional negotiation for dynamic data chunking are described herein. A set of available features for a memory subsystem. The set of available features including latency of buffer locations of the memory subsystem. An indication of a first latency requirement of a first data consumer and a second latency requirement of a second data consumer may be obtained. A first buffer location of the memory subsystem for a data stream based on the first latency requirement may be negotiated with the first data consumer. A second buffer location of the memory subsystem for the data stream based on the second latency requirement may be negotiated with the second data consumer. An indication of the first buffer location may be provided to the first data consumer and an indication of the second buffer location may be provided to the second data consumer.

First claim

What is claimed is:

1. A memory control device for dynamic data chunking, the memory control device comprising:
at least one processor; and
memory including instructions that, when executed by the at least one processor, cause the at least one processor to:
identify a set of available features for a memory subsystem, the set of available features including latency of buffer locations of the memory subsystem;
obtain an indication of a first latency requirement of a first data consumer and a second latency requirement of a second data consumer;
identify, for the first data consumer, a first buffer location of the memory subsystem for a data stream based on the first latency requirement, wherein identification of the first buffer location includes identifying that the first buffer location is compatible with the first latency requirement;
identify, for the second data consumer, a second buffer location of the memory subsystem for the data stream based on the second latency requirement wherein identification of the second buffer location includes identifying that the second buffer location is compatible with the second latency requirement; and
provide an indication of the first buffer location to the first data consumer and an indication of the second buffer location to the second data consumer.

2. The memory control device of claim 1 , wherein the instructions to identify the second buffer location include instructions to determine the second latency requirement is compatible with the first buffer location, wherein the second buffer location is the same as the first buffer location and further comprising instructions to output the data stream to the first buffer location, wherein the first buffer location uses a first data chunk size.

3. The memory control device of claim 1 , wherein the first data consumer is a first channel of a multiplex data consumer and the second data consumer is a second channel of the multiplex data consumer.

4. The memory control device of claim 1 , wherein the instructions to identify the second buffer location include instructions to determine the second latency requirement is incompatible with the first buffer location and further comprising instructions to:
output the data stream to the first buffer location, wherein the first buffer location has a first data chunk size; and
output the data stream to the second buffer location, wherein the second buffer location has a second data chunk size.

5. The memory control device of claim 4 , wherein the first buffer location is a sub-frame latency buffer of a low-power memory device and the second buffer location is a full-frame latency buffer of a system-level memory device.

6. The memory control device of claim 4 , wherein the first buffer location is a compressed portion of a full-frame latency buffer of a system-level memory device and the second buffer location is an uncompressed portion of the full-frame latency buffer.

7. The memory control device of claim 1 , further comprising instructions to:
obtain compression features for the buffer locations of the memory subsystem; and
identify a first compression requirement for the first data consumer and a second compression requirement for the second data consumer, wherein the instructions to identify the first buffer location and the second buffer location include instructions to evaluate the first compression requirement and the second compression requirement respectively.

8. The memory control device of claim 1 , further comprising instructions to:
obtain data chunk size features for the buffer locations of the memory subsystem; and
identify a first data chunk size requirement for the first data consumer and a second data chunk size requirement for the second data consumer, wherein the instructions to identify the first buffer location and the second buffer location include instructions to evaluate the first data chunk size requirement and the second data chunk size requirement respectively.

9. The memory control device of claim 1 , wherein the first data consumer is a member of a first data consumer group and the second data consumer is a member of a second data consumer group and the instructions further comprising instructions to:
determine a first group latency requirement for the first data consumer group and a second group latency requirement for the second data consumer group, wherein the instructions to identify the first buffer location and the second buffer location include instructions to evaluate the first group latency requirement and the second group latency requirement respectively.

10. At least one non-transitory computer readable medium including instructions for dynamic data chunking that when executed by at least one processor, cause the at least one processor to:
identify a set of available features for a memory subsystem, the set of available features including latency of buffer locations of the memory subsystem;
obtain an indication of a first latency requirement of a first data consumer and a second latency requirement of a second data consumer;
identify, for the first data consumer, a first buffer location of the memory subsystem for a data stream based on the first latency requirement, wherein identification of the first buffer location includes identifying that the first buffer location is compatible with the first latency requirement;
identify, for the second data consumer, a second buffer location of the memory subsystem for the data stream based on the second latency requirement, wherein identification of the first buffer location includes identifying that the first buffer location is compatible with the first latency requirement; and
provide an indication of the first buffer location to the first data consumer and an indication of the second buffer location to the second data consumer.

11. The at least one computer readable medium of claim 10 , wherein the instructions to identify the second buffer location include instructions to determine the second latency requirement is compatible with the first buffer location, wherein the second buffer location is the same as the first buffer location and further comprising instructions to output the data stream to the first buffer location, wherein the first buffer location uses a first data chunk size.

12. The at least one computer readable medium of claim 10 , wherein the first data consumer is a first channel of a multiplex data consumer and the second data consumer is a second channel of the multiplex data consumer.

13. The at least one computer readable medium of claim 10 , wherein the instructions to identify the second buffer location include instructions to determine the second latency requirement is incompatible with the first buffer location and further comprising instructions to:
output the data stream to the first buffer location, wherein the first buffer location has a first data chunk size; and
output the data stream to the second buffer location, wherein the second buffer location has a second data chunk size.

14. The at least one computer readable medium of claim 10 , further comprising instructions to:
obtain compression features for the buffer locations of the memory subsystem; and
identify a first compression requirement for the first data consumer and a second compression requirement for the second data consumer, wherein the instructions to identify the first buffer location and the second buffer location include instructions to evaluate the first compression requirement and the second compression requirement respectively.

15. The at least one computer readable medium of claim 10 , f

Assignees

• Intel Corp

Inventors

• Yasman Eugene
• Ain-Kedem Liron
• Gerber Nir

Classifications

• H04L47/00 Primary

  Traffic control in data switching networks (arrangements for detecting or preventing errors in the information received H04L1/00) · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0631 Primary

  by allocating resources to storage systems · CPC title