Performance tests of capacitors

Patent metadata

Field	Value
Publication number	US-10914790-B2
Application number	US-201815881031-A
Country	US
Kind code	B2
Filing date	Jan 26, 2018
Priority date	Jan 26, 2018
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

Example implementations relate to performance tests of capacitors. In some examples, a controller may comprise a processing resource to measure a change in voltage of a capacitor of a circuit in response to the controller entering a test mode, determine, based on the measured change in the voltage and an impedance of the circuit, a capacitance of the capacitor, compare the determined capacitance of the capacitor to a predetermined capacitance value, and determine, based on the comparison, a performance of the capacitor.

First claim

What is claimed:

1. A controller, comprising:
a processing resource; and
a memory resource storing machine-readable instructions to cause the processing resource to:
detect when the controller enters a test mode that charges or discharges a capacitor from a first voltage to at least a predetermined second voltage;
count cycles of a clock while measuring a voltage of the capacitor during the charge or discharge;
when the capacitor reaches the predetermined second voltage, derive the time of change in the voltage from the counted cycles of the clock;
determine, based on the time of change in the voltage and a known impedance of a circuit coupled to the capacitor, a capacitance of the capacitor;
compare the determined capacitance of the capacitor to a predetermined capacitance value; and
determine, based on the comparison, a performance of the capacitor.

2. The controller of claim 1 , wherein the test mode comprises a discharge of the capacitor.

3. The controller of claim 2 , wherein the instructions are executed by the processor to measure a voltage decay from the first voltage to the predetermined second voltage as a result of the discharge of the capacitor.

4. The controller of claim 1 , wherein the test mode comprises a charge of the capacitor.

5. The controller of claim 1 , wherein the capacitor is built into a computing device, and wherein the controller enters the test mode during a powering-off process of the computing device.

6. The controller of claim 1 , wherein the capacitor is built into a computing device, and wherein the controller enters the test mode during a powering-on process of the computing device.

7. The controller of claim 1 , wherein the controller is internal to a voltage regulator.

8. The controller of claim 1 , wherein the controller is external to a voltage regulator.

9. A non-transitory machine-readable storage medium having stored thereon machine-readable instructions to cause a computer processor to:
begin counting clock cycles while monitoring a voltage of a capacitor when a controller, entering a test mode, begins charging or discharging the capacitor from a first voltage;
capture the number of counted clock cycles when the capacitor reaches a predetermined second voltage;
derive a time of change in voltage of the capacitor from the number of counted clock cycles;
determine, based on the time of change in the voltage and a known impedance of a circuit coupled to the capacitor, a capacitance of the capacitor;
compare the determined capacitance of the capacitor to a predetermined capacitance value;
determine, in response to the determined capacitance being above the predetermined capacitance value, the capacitor as having passed the test; and
determine, in response to the determined capacitance being below the predetermined capacitance value, the capacitor as having failed the test.

10. The medium of claim 9 , wherein the instructions comprise instructions to measure a time of discharge of the capacitor.

11. The medium of claim 9 , wherein the instructions further comprise instructions to measure a time of charge of the capacitor after applying a predetermined input current.

12. The medium of claim 11 , further comprising instructions to determine the capacitance of the capacitor using the impedance of the circuit, the time of charge, and the predetermined input current.

13. The medium of claim 9 , wherein the predetermined second voltage is 0.368 times a voltage at which the capacitor normally operates.

14. The medium of claim 9 , wherein the predetermined second voltage is 0.63 times a voltage at which the capacitor normally operates.

15. The medium of claim 9 , wherein a frequency of the clock cycles is greater than 100*(1/Tau), wherein Tau equals the known impedance multiplied by the predetermined capacitance value.

16. A method, comprising:
causing a controller of a voltage regulator to enter a capacitance test mode that charges or discharges a capacitor from a first voltage to at least a predetermined second voltage;
measuring, by the controller, a time of change in voltage of the capacitor when the capacitor reaches the predetermined second voltage;
determining, by the controller, based on the measured time of change in the voltage and a known impedance of a circuit coupled to the capacitor, a capacitance of the capacitor;
comparing, by the controller, the determined capacitance of the capacitor to a predetermined capacitance value;
determining, by the controller, in response to the determined capacitance being within a specified tolerance of the predetermined capacitance value, the capacitor as having passed the test; and
determining, by the controller in response to the determined capacitance being outside the specified tolerance of the predetermined capacitance value, the capacitor as having failed the test.

17. The method of claim 16 , wherein the method further includes changing, in response to the capacitor having failed the test, controller parameters to enable the voltage regulator to function correctly with the capacitor that failed the test.

18. The method of claim 17 , wherein the controller parameters include an input current.

19. The method of claim 16 , wherein the method further includes generating, in response to the capacitor having failed the test, an alert.

20. The method of claim 16 , wherein the specified tolerance of the predetermined capacitance value is nonzero for higher values of the determined capacitance and zero for lower values of the determined capacitance.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Yates Kirk
• Bemat Mohamed Amin

Classifications

• G01R31/64 Primary

  Testing of capacitors · CPC title

• G04C10/00

  Arrangements of electric power supplies in time-pieces {(Mounting, assembling of components G04C3/008)} · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title