Digital in-pixel read-out integrated circuit including residue-to-counter calibration

US10911705B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10911705-B2
Application numberUS-201916427968-A
CountryUS
Kind codeB2
Filing dateMay 31, 2019
Priority dateMay 31, 2019
Publication dateFeb 2, 2021
Grant dateFeb 2, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A digital pixel circuit includes a unit cell configured to accumulate an electrical charge during a frame. The electrical charge is proportional to a light intensity of a light signal that is detected at a location in a field of view of the unit cell. An image processing unit is in signal communication with the unit cell. The image processing unit is configured to determine a total charge based on a plurality of accumulated charges over a plurality of sequential frames, and to determine an indication of the light intensity of light at the location based on the total charge. The unit cell is configured to operate in a first mode to accumulate the electrical charges over the plurality of sequential frames, and a second mode to perform a calibration operation that calibrates the unit cell based on the electrical charge accumulated during a single frame among the plurality of frames.

First claim

Opening claim text (preview).

What is claimed is: 1. A digital pixel circuit comprising: a unit cell configured to accumulate an electrical charge during a frame, the electrical charge being proportional to a light intensity of a light signal that is detected at a location in a field of view of the unit cell, wherein the unit cell comprises: an image detector that includes a light sensor configured to detect the light signal and an energy storage device configured to accumulate the electrical charge; and a digital readout integrated circuit (DROIC) including a disable circuit in signal communication with the image detector; and an image processing unit in signal communication with the unit cell, the image processing unit configured to determine a total charge based on a plurality of accumulated charges, and to determine an indication of the light intensity of light at the location based on the total charge, wherein the unit cell is configured to operate in a first mode to accumulate the electrical charges, and to operate in a second mode to perform a calibration operation that calibrates the unit cell based on the electrical charge accumulated, wherein the disable circuit includes a switch connected in parallel with the energy storage device and configured to selectively invoke the first mode and the second mode, and wherein the switch is activated in response to invoking the second mode such that the switch delivers a bias voltage across the energy storage device to prevent the energy storage device from discharging. 2. The digital pixel circuit of claim 1 , wherein the calibration operation is performed prior to completing a final frame. 3. The digital pixel circuit of claim 1 , wherein the disable circuit is configured to connect the light sensor to the energy storage device in response to invoking the first mode, and to disconnect the light sensor from the energy storage device in response to invoking the second mode. 4. The digital pixel circuit of claim 3 , wherein the disable circuit is further configured to allow the energy storage device to discharge in response to the electrical charge reaching a charge threshold level while operating in the first mode, and wherein the disable circuit is configured to prevent the energy storage device from discharging while operating in the second mode. 5. The digital pixel circuit of claim 4 , wherein the image sensor is a photodiode, and the energy storage device is a capacitor. 6. The digital pixel circuit of claim 1 , wherein the switch is deactivated in response to invoking the first mode such that the switch disconnects the bias voltage across the energy storage device to allow the energy storage device to discharge in response to reaching the charge threshold level. 7. A unit cell included in a digital pixel circuit, the unit cell comprising: an image detector that includes a light sensor configured to detect a light signal and an energy storage device configured to accumulate an electrical charge during a frame; and a digital readout integrated circuit (DROIC) including a disable circuit in signal communication with the image detector, the disable circuit configured to selectively invoke a first mode configured to determine a total electrical charge of the DROIC based on a plurality of accumulated electrical charges, and a second mode configured to calibrate the DROIC based on an accumulated charge, wherein the disable circuit includes a switch connected in parallel with the energy storage device, and wherein the switch is activated in response to invoking the second mode such that the switch delivers a bias voltage across the energy storage device to prevent the energy storage device from discharging. 8. The unit cell of claim 7 , wherein the disable circuit is configured to connect the light sensor to the energy storage device in response to invoking the first mode, and to disconnect the light sensor from the energy storage device in response to invoking the second mode. 9. The unit cell of claim 8 , wherein the disable circuit is further configured to allow the energy storage device to discharge in response to the electrical charge reaching a charge threshold level while operating in the first mode, and wherein the disable circuit is configured to prevent the energy storage device from discharging while operating in the second mode. 10. The unit cell of claim 9 , wherein the image sensor is a photodiode, and the energy storage device is a capacitor. 11. The unit cell of claim 7 , wherein the switch is deactivated in response to invoking the first mode such that the switch disconnects the bias voltage across the energy storage device to allow the energy storage device to discharge in response to reaching the charge threshold level. 12. A method of operating a unit cell included in a digital pixel circuit, the method comprising: accumulating an electrical charge, via a unit cell, during a frame, the electrical charge being proportional to a light intensity of a light signal that is detected at a location in a field of view of the unit cell; and determining, via an image processing unit in signal communication with the unit cell, a total charge based on a plurality of accumulated charges; invoking a first mode of the unit cell to accumulate the plurality of electrical charges; invoking a second mode of the unit cell to perform a calibration operation that calibrates the unit cell based on the electrical charge; connecting the light sensor to the energy storage device via a disable circuit in response to invoking the first mode; and disconnecting the light sensor from the energy storage device via the disable circuit in response to invoking the second mode, wherein the connecting and disconnecting includes: activating a switch in response to invoking the second mode to deliver a bias voltage across the energy storage device to prevent the discharging; and deactivating the switch in response to invoking the first mode to disconnect the bias voltage across the energy storage device to allow the discharge, and wherein the switch is connected in parallel with the energy storage device. 13. The method of claim 12 , further comprising: allowing allow the energy storage device to discharge via the disable circuit in response to the electrical charge reaching a charge threshold level while operating in the first mode; and preventing the energy storage device from discharging via the disable circuit while operating in the second mode.

Assignees

Inventors

Classifications

  • H04N25/77Primary

    Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

  • Control of the integration time · CPC title

  • Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

  • comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD] · CPC title

  • H04N25/60Primary

    Noise processing, e.g. detecting, correcting, reducing or removing noise · CPC title

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What does patent US10911705B2 cover?
A digital pixel circuit includes a unit cell configured to accumulate an electrical charge during a frame. The electrical charge is proportional to a light intensity of a light signal that is detected at a location in a field of view of the unit cell. An image processing unit is in signal communication with the unit cell. The image processing unit is configured to determine a total charge based…
Who is the assignee on this patent?
Raytheon Co
What technology area does this patent fall under?
Primary CPC classification H04N25/77. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 02 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).