Self-tuning zero current detection circuit

Patent metadata

Field	Value
Publication number	US-10910946-B2
Application number	US-201816144961-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

An apparatus has a comparator circuitry (e.g., auto-zero comparator) with a first input, a second input, a third input; and an output; a first device (e.g., a low-side switch) coupled to the first and second inputs of the comparator; and a circuitry (e.g., a self-tuning logic) to generate a digital code which represents a comparator offset adjustment with reference to detection of current through a second device (e.g., an inductor), wherein the digital code (e.g., a multibit digital signal) is provided to the third input of the comparator circuitry.

First claim

It is claimed:

1. An apparatus comprising: a comparator circuitry having a first input, a second input, and a third input, wherein the comparator circuitry comprises a digital-to-analog converter (DAC) having an input coupled to the third input of the comparator circuitry; a first device coupled to the first and second inputs of the comparator circuitry, wherein an output of the DAC is switchably coupled to a terminal of a capacitor via a switch, wherein the switch is controllable by a first signal derived off a second signal that controls the first device; and a circuitry to generate a digital code which represents a comparator offset adjustment with reference to detection of current through a second device, wherein the digital code is provided to the third input of the comparator circuitry.

2. The apparatus of claim 1 , wherein the comparator circuitry comprises:
first and second AC coupling capacitors coupled to the first and second inputs via first and second controllable switches, respectively; wherein the
capacitor is coupled to one of the first or second AC coupling capacitors via a third controllable switch.

3. The apparatus of claim 2 , wherein the comparator circuitry comprises a fourth input to receive a common mode voltage, and wherein the common mode voltage is coupled to the first and second AC coupling capacitors.

4. The apparatus of claim 1 , wherein the comparator circuitry is power gated.

5. The apparatus of claim 1 , wherein the first device is part of a low-side switch of a DC-DC converter.

6. The apparatus of claim 1 , wherein the second device is an inductor.

7. The apparatus of claim 1 , wherein the circuitry comprises:
a first transistor coupled to the second device;
a second transistor coupled in series with the first transistor;
a buffer coupled to the first and second transistors; and
a flip-flop coupled to the buffer, wherein a clock input of the flip-flop is controllable by a signal received by a low-side switch, wherein the first device is part of the low-side switch, and wherein an output of the flip-flop is to provide the detection of current through the second device.

8. The apparatus of claim 7 , wherein the circuitry includes a counter to count up or down a value of the digital code according to the output of the flip-flop.

9. The apparatus of claim 7 , wherein a gate terminal of the first transistor is coupled to a power supply node that is to provide half of an input supply voltage.

10. The apparatus of claim 7 , wherein a gate terminal of the second transistor is coupled to ground.

11. The apparatus of claim 7 , wherein the signal received by the low-side switch is delayed before it is provided as the clock input for the flip-flop.

12. An apparatus comprising:
a high-side switch coupled to a first power supply rail;
a low-side switch coupled in series with the high-side switch, wherein the low-side switch is coupled to ground;
an inductor coupled to the high-side and low-side switches;
a comparator circuitry having a first input, a second input, and a third input, wherein the first and second inputs are coupled to the low-side switch, wherein a digital code is provided to the third input to adjust an offset of the comparator circuitry according to a current through the inductor, wherein the comparator comprises a digital-to-analog converter (DAC) having an input coupled to the third input of the comparator circuitry, wherein an output of the DAC is switchably coupled to a terminal of a capacitor via a switch, and wherein the switch is controllable by a first signal derived off a second signal that controls the low-side switch;
a current detection circuitry to detect current through the inductor and to provide that detection as an output; and
circuitry to receive the output of the current detection circuitry and to adjust the digital code according to the output of the current detection circuitry.

13. The apparatus of claim 12 , wherein current detection circuitry comprises:
a first transistor coupled to the inductor;
a second transistor coupled in series with the first transistor;
a buffer coupled to the first and second transistors; and
a flip-flop coupled to the buffer, wherein a clock input of the flip-flop is controllable by a signal received by the low-side switch.

14. The apparatus of claim 12 , wherein the comparator circuitry comprises:
first and second AC coupling capacitors coupled to the first and second inputs via first and second controllable switches, respectively; wherein the
capacitor is coupled to one of the first or second AC coupling capacitors via a third controllable switch.

15. The apparatus of claim 14 , wherein the comparator circuitry comprises a fourth input to receive a common mode voltage, and wherein the common mode voltage is coupled to the first and second AC coupling capacitors.

16. The apparatus of claim 12 , wherein the comparator circuitry is power gated.

17. A system comprising: a memory; a processor coupled to the memory, wherein the processor includes a DC-DC converter which comprises: a comparator circuitry having a first input, a second input, and a third input, wherein the comparator circuitry comprises a digital-to-analog converter (DAC) having an input coupled to the third input of the comparator circuitry; a first device coupled to the first and second inputs of the comparator circuitry, wherein an output of the DAC is switchably coupled to a terminal of a capacitor via a switch, wherein the switch is controllable by a first signal derived off a second signal that controls the first device; and a circuitry to generate a digital code which represents a comparator offset adjustment with reference to detection of current through a second device, wherein the digital code is provided to the third input of the comparator circuitry; and a wireless interface to allow the processor to communicate with another device.

18. The system of claim 17 , wherein the comparator circuitry comprises:
first and second AC coupling capacitors coupled to the first and second inputs via first and second controllable switches, respectively; wherein the
capacitor is coupled to one of the first or second AC coupling capacitors via a third controllable switch.

19. The system of claim 18 , wherein the circuitry comprises:
a first transistor coupled to the second device;
a second transistor coupled in series with the first transistor;
a buffer coupled to the first and second transistors; and
a flip-flop coupled to the buffer, wherein a clock input of the flip-flop is controllable by a signal received by a low-side switch, wherein the first device is part of the low-side switch, and wherein an output of the flip-flop is to provide the detection of current through the second device.

20. The system of claim 19 , wherein the circuitry includes a counter to count up or down a value of the digital code according to the output of the flip-flop.

Assignees

• Intel Corp

Inventors

• Schaef Christopher

Classifications

• H10D1/20

  Inductors · CPC title

• H02M1/0058

  by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero (using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826) · CPC title

• H02M3/1588

  comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title