Array substrate, manufacturing method thereof and display panel

Patent metadata

Field	Value
Publication number	US-10910411-B2
Application number	US-201916504780-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Nov 1, 2018
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

An array substrate is provided that includes a plurality of sub-pixels arranged in a matrix. Each of the sub-pixels includes a substrate, a gate, a source and a drain, and a common electrode on the substrate, a passivation layer on a side of the common electrode facing away from the substrate, and a pixel electrode on a side of the passivation layer facing away from the substrate. The array substrate further includes a common electrode line, the common electrode line being formed of a same material in a same layer as the source and the drain. The common electrode is in direct electrical contact with the common electrode line. The pixel electrode and the drain are electrically connected through a via hole in the passivation layer. A display panel and a method for manufacturing an array substrate are further provided.

First claim

The invention claimed is:

1. An array substrate comprising a plurality of sub-pixels arranged in a matrix, each sub-pixel of the plurality of sub-pixels comprising:
a substrate;
a gate, a source and a drain, and a common electrode on the substrate;
a passivation layer on a side of the common electrode facing away from the substrate; and
a pixel electrode on a side of the passivation layer facing away from the substrate,
wherein the array substrate further comprises a common electrode line, the common electrode line comprises a same material and is in a same layer as the source and the drain,
wherein the common electrode is in direct electrical contact with the common electrode line,
wherein the pixel electrode and the drain are electrically connected through a via hole in the passivation layer,
wherein the array substrate further comprises a data line, the data line extends in an extension direction of the common electrode line, and
wherein the common electrode line is electrically connected to common electrodes of sub-pixels arranged in the extension direction of the common electrode line.

2. The array substrate according to claim 1 , wherein the common electrode overlaps at least a portion of the common electrode line.

3. An array substrate comprising a plurality of sub-pixels arranged in a matrix, each sub-pixel of the plurality of sub-pixels comprising:
a substrate;
a gate, a source and a drain, and a common electrode on the substrate;
a passivation layer on a side of the common electrode facing away from the substrate; and
a pixel electrode on a side of the passivation layer facing away from the substrate,
wherein the array substrate further comprises a common electrode line, the common electrode line comprises a same material and is in a same layer as the source and the drain,
wherein the common electrode is in direct electrical contact with the common electrode line, and
wherein the pixel electrode and the drain are electrically connected through a via hole in the passivation layer,
wherein the array substrate further comprises:
a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, wherein each of the gate lines is electrically connected to gates of a plurality of sub-pixels arranged in the first direction, and wherein each of the data lines is electrically connected to sources of a plurality of sub-pixels arranged in the second direction; and
a shielding line, wherein an orthographic projection of the shielding line on the substrate overlaps orthographic projections of one or more of the gate lines and the data lines on the substrate.

4. The array substrate according to claim 3 , wherein the shielding line comprises a same material in a same layer as the pixel electrode.

5. The array substrate according to claim 3 , wherein the shielding line is electrically connected to the common electrode line.

6. The array substrate according to claim 1 ,
wherein the array substrate further comprises a peripheral area surrounding a display area,
wherein the peripheral area comprises a common electrode auxiliary line,
wherein the common electrode auxiliary line is electrically connected to the common electrode line.

7. The array substrate according to claim 6 , further comprising:
a plurality of gate lines extending in a first direction and a plurality of data lines extending in the extension direction of the common electrode line, the extension direction of the common electrode line is a second direction, wherein each of the gate lines is electrically connected to gates of a plurality of sub-pixels arranged in the first direction, and wherein each of the data lines is electrically connected to sources of a plurality of sub-pixels arranged in the second direction; and
a shielding line, wherein an orthographic projection of the shielding line on the substrate overlaps orthographic projections of one or more of the gate lines and the data lines on the substrate,
wherein the plurality of data lines are parallel to a plurality of common electrode lines comprising the common electrode line, and
wherein the common electrode auxiliary line is electrically connected to the shielding line.

8. An array substrate comprising a plurality of sub-pixels arranged in a matrix, each sub-pixel of the plurality of sub-pixels comprising:
a substrate;
a gate, a source and a drain, and a common electrode on the substrate;
a passivation layer on a side of the common electrode facing away from the substrate; and
a pixel electrode on a side of the passivation layer facing away from the substrate,
wherein the array substrate further comprises a common electrode line, the common electrode line comprises a same material and is in a same layer as the source and the drain,
wherein the common electrode is in direct electrical contact with the common electrode line, and
wherein the pixel electrode and the drain are electrically connected through a via hole in the passivation layer,
wherein the pixel electrode comprises a first slit electrode, and
wherein the common electrode comprises one of a platelike electrode and a second slit electrode.

9. A display panel comprising the array substrate according to claim 1 .

10. The display panel according to claim 9 , wherein the common electrode overlaps at least a portion of the common electrode line.

11. The display panel according to claim 9 , further comprising:
a plurality of gate lines extending in a first direction and a plurality of data lines extending in the extension direction of the common electrode line, the extension direction of the common electrode line is a second direction, wherein each of the gate lines is electrically connected to gates of a plurality of sub-pixels arranged in the first direction, and wherein each of the data lines is electrically connected to sources of a plurality of sub-pixels arranged in the second direction; and
a shielding line, wherein an orthographic projection of the shielding line on the substrate overlaps orthographic projections of one or more of the gate lines and the data lines on the substrate.

12. The display panel according to claim 11 , wherein the shielding line is formed of a same material in a same layer as the pixel electrode.

13. The display panel according to claim 11 , wherein the shielding line is electrically connected to the common electrode line.

14. The display panel according to claim 9 ,
wherein the array substrate further comprises a peripheral area surrounding a display area, the peripheral area comprising a common electrode auxiliary line, and
wherein the common electrode auxiliary line is electrically connected to the common electrode line.

15. The display panel according to claim 14 , further comprising:
a plurality of gate lines extending in a first direction and a plurality of data lines extending in the extension direction of the common electrode line, the extension direction of the common electrode line is a second direction, wherein each of the gate lines is electrically connected to gates of a plurality of sub-pixels arranged in the first direction, and wherein each of the data lines is electrically connected to sources of a plurality of sub-pixels arranged in the second direction; and
a shielding line, wherein an orthographic projection of the shielding line on the substrate overlaps orthographic projections of one or more of the gate lines and the data lines on the substrate,
wherein the plurality of data lines are parallel to a plurality of common electrode lines comprising the common electrode line, and
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Assignees

• Boe Technology Group Co Ltd

Inventors

• Choi Hyunsic

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title