Bandgap reference circuit
US-9612606-B2 · Apr 4, 2017 · US
Method for stabilizing bandgap voltage
US10909299B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-10909299-B1 |
| Application number | US-202016881020-A |
| Country | US |
| Kind code | B1 |
| Filing date | May 22, 2020 |
| Priority date | Apr 27, 2020 |
| Publication date | Feb 2, 2021 |
| Grant date | Feb 2, 2021 |
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Abstract
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A method for stabilizing bandgap voltage includes the steps of: providing a first layout pattern designated with a first voltage; reducing a critical dimension of the first layout pattern for generating a second layout pattern corresponding to a second voltage; matching the second voltage with a target voltage; and then outputting the second layout pattern to a mask. Preferably, the first layout pattern and the second layout pattern include polysilicon resistor patterns.
First claim
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What is claimed is: 1. A method for stabilizing bandgap voltage, comprising: providing a first layout pattern designated with a first voltage; reducing a critical dimension of the first layout pattern for generating a second layout pattern corresponding to a second voltage; matching the second voltage with a target voltage; and outputting the second layout pattern to a mask. 2. The method of claim 1 , wherein the first layout pattern and the second layout pattern comprise polysilicon resistor patterns. 3. The method of claim 1 , further comprising reducing a width of the first layout pattern for generating the second layout pattern. 4. The method of claim 3 , further comprising reducing the width of the first layout pattern for generating the second layout pattern and a third layout pattern. 5. The method of claim 4 , further comprising reducing the width of the first layout pattern between 2% to 4% for generating the second layout pattern. 6. The method of claim 4 , further comprising reducing the width of the first layout pattern between 4% to 6% for generating the third layout pattern. 7. The method of claim 4 , wherein the second layout pattern corresponds to the second voltage and the third layout pattern corresponds to a third voltage. 8. The method of claim 7 , further comprising matching the third voltage with the target voltage. 9. The method of claim 4 , further comprising reducing the width of the first layout pattern for generating the second layout pattern, the third layout pattern, and a fourth layout pattern. 10. The method of claim 9 , further comprising reducing the width of the first layout pattern between 6% to 8% for generating the fourth layout pattern.
Assignees
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Classifications
- G03F1/76Primary
Patterning of masks by imaging · CPC title
- G06F30/392Primary
Floor-planning or layout, e.g. partitioning or placement · CPC title
Design optimisation · CPC title
Physical level, e.g. placement or routing · CPC title
Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title
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- What does patent US10909299B1 cover?
- A method for stabilizing bandgap voltage includes the steps of: providing a first layout pattern designated with a first voltage; reducing a critical dimension of the first layout pattern for generating a second layout pattern corresponding to a second voltage; matching the second voltage with a target voltage; and then outputting the second layout pattern to a mask. Preferably, the first layou…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification G03F1/76. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 02 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).