Multi-layer ceramic electronic component and method of producing the same

Patent metadata

Field	Value
Publication number	US-10903007-B2
Application number	US-201816194971-A
Country	US
Kind code	B2
Filing date	Nov 19, 2018
Priority date	Nov 30, 2017
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

A multi-layer ceramic electronic component includes a ceramic body including a multi-layer unit, a side margin, and ridges. The multi-layer unit includes a capacitance forming unit including ceramic layers laminated in a first direction and internal electrodes disposed between the ceramic layers, a cover that covers the capacitance forming unit in the first direction, and a side surface facing in a second direction orthogonal to the first direction. The side margin covers the side surface. The ridges are rounded and extend in a third direction orthogonal to the first and second directions. The capacitance forming unit includes a first region disposed at a center portion in the first direction, and a second region disposed between the cover and the first region, end portions of the internal electrodes in the second direction in the second region being positioned inward in the second direction relative to those in the first region.

First claim

What is claimed is:

1. A multi-layer ceramic electronic component, comprising
a ceramic body including
a multi-layer unit including
a capacitance forming unit including
ceramic layers laminated in a first direction, and
internal electrodes disposed between the ceramic layers,

a cover that covers the capacitance forming unit in the first direction, and
a side surface that faces in a second direction orthogonal to the first direction,

the internal electrodes being exposed from the side surface,
a side margin that covers the side surface of the multi-layer unit, and
first ridges being rounded and extending in a third direction orthogonal to the first direction and the second direction,

the capacitance forming unit including a first region and a second region, the first region being disposed at a center portion in the first direction, the second region being disposed between the cover and the first region, end portions of the internal electrodes in the second direction in the second region being positioned inward in the second direction relative to end portions of the internal electrodes in the second direction in the first region,
wherein the internal electrodes have, in the second region, dimensions in the second direction that gradually decrease from the first region toward the cover,
wherein the multi-layer unit further includes rounded second ridges extending in the third direction, each of the second ridges including end portions of the cover and the second region in the second direction, each of the second ridges formed at the boundary with the side margin,
wherein the first ridges are formed by the side margins and cover the second ridges, and
wherein the first ridges and the second ridges are respectively curved from a position inward in the second direction relative to the end portions of the internal electrodes in the second region.

2. The multi-layer ceramic electronic component according to claim 1 , wherein
the side margin has a dimension in the second direction that is equal to or larger than 10 μm at a position adjacent to the second region.

3. The multi-layer ceramic electronic component according to claim 1 , wherein
a difference (Dmax−Dmin) between a maximum thickness Dmax of the side margin and a minimum thickness Dmin of the side margin is equal to or smaller than 10 μm at a position in the second region, the position being adjacent to the internal electrodes in the second direction.

4. The multi-layer ceramic electronic component according to claim 1 , wherein
the end portions of the internal electrodes in the second direction have variations in position that fall within a range equal to or smaller than 0.5 μm in the first region.

5. A method of producing a multi-layer ceramic electronic component, comprising:
producing a multi-layer chip including
a capacitance forming unit including
ceramic layers laminated in a first direction, and
internal electrodes disposed between the ceramic layers,

a cover that covers the capacitance forming unit in the first direction, and
a side surface that faces in a second direction orthogonal to the first direction, the internal electrodes being exposed from the side surface;

chamfering the multi-layer chip; and, after chamfering,
forming a side margin on the side surface of the chamfered multi-layer chip.

6. The method of producing a multi-layer ceramic electronic component according to claim 5 , wherein
the multi-layer chip is chamfered by barrel polishing.

Assignees

• Taiyo Yuden Kk

Inventors

• Ono Ryo
• Fukuoka Tetsuhiko
• Kusumoto Shoji
• Kono Akihiko

Classifications

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/248

  the terminals embracing or surrounding the capacitive element, e.g. caps (H01G4/252 takes precedence) · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/1227

  based on alkaline earth titanates · CPC title

• H01G4/1236

  based on zirconium oxides or zirconates (H01G4/1263 takes precedence) · CPC title