Transient current-protected threshold switching devices systems and methods

Patent metadata

Field	Value
Publication number	US-10902911-B2
Application number	US-201916676330-A
Country	US
Kind code	B2
Filing date	Nov 6, 2019
Priority date	Dec 26, 2015
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory cell comprising:
a select device (SD) material; and
a resistive memory material electrically coupled to the SD material;

a word line (WL) coupled to the memory cell;
a bit line (BL) coupled to the memory cell, such that each memory cell is addressed by the combination of the WL and the BL; and
circuitry electrically coupled to the WL and BL, the circuitry configured to:
select the memory cell to be read by selecting the combination of WL and BL;
apply a WL read bias voltage (WLV) to the WL;
uncouple the WL from the WLV to float the WL;
apply a BL read bias voltage (BLV) to the BL, such that the BLV and the WLV at the floating WL activate the memory cell; and
recouple the WL to the WLV to deliver a repair current to the memory cell.

2. The apparatus of claim 1 , further comprising a memory controller and circuitry coupled to the WL and the BL to address the memory cell.

3. The apparatus of claim 1 , wherein the circuitry comprises:
a WL select switch coupled between the WLV and the WL, the WL select switch operable to gate coupling of the WLV to the WL; and
a control input coupled to the WL select switch to operate the WL select switch.

4. The apparatus of claim 3 , wherein the BL is to activate the WL select switch to couple the WLV to the WL in response to application of the BLV to the BL.

5. The apparatus of claim 4 , wherein the circuitry comprises a bypass switch gated by the BLV, wherein activation of the bypass switch delivers the WLV from the floating WL to gate the WL select switch, thereby coupling the WLV to the WL.

6. The apparatus of claim 5 , wherein the bypass switch comprises an NMOS transistor.

7. The apparatus of claim 3 , wherein the circuitry further comprises a WL device select switch coupled to the WL between the WL select switch and a power source, wherein the WL device select switch is gated by application of the WLV to the WL device select switch.

8. The apparatus of claim 3 , wherein the circuitry further comprises a BL device select switch coupled to the BL between the BL and a power source, wherein the BL device select switch is gated by application of the BLV to the BL device select switch.

9. The apparatus of claim 1 , further comprising:
a plurality of resistive memory elements arranged in an array;
a plurality of WLs coupled to groups of resistive memory elements across the array;
a plurality of BLs coupled to groups of resistive memory elements across the array, such that each resistive memory element is addressed in the array by a unique combination of a WL and a BL; and
a controller coupled to the plurality of WLs and the plurality of BLs to address the plurality of resistive memory elements in the array.

10. The apparatus of claim 9 , wherein the plurality of resistive memory elements separately comprise a resistive memory material coupled adjacent to the resistive memory material of the memory cell and between the WL and the BL.

11. The apparatus of claim 1 , the resistive memory material comprises phase change memory material.

12. A method, comprising:
selecting a memory cell including a resistive memory material having a word line (WL) and a bit line (BL) electrically coupled across the resistive memory material;
applying a WL read bias voltage (WLV) to the WL;
uncoupling the WL from the WLV to float the WL;
applying a BL read bias voltage (BLV) to the BL, such that the BLV and the WLV at the floating WL activate the memory cell; and
reapplying the WLV to the WL to deliver a repair current to the memory cell.

13. The method of claim 12 , wherein applying the WLV to the WL further comprises activating a WL select switch coupled between the WLV and the WL.

14. The method of claim 13 , wherein applying the BLV to the BL is to activate the WL select switch to reapply the WLV to the WL.

15. The method of claim 14 , wherein applying the BLV to the BL activates a bypass switch that delivers current from the floating WL to the WL select switch to reapply the WLV to the WL.

16. The method of claim 12 , the resistive memory material comprises phase change memory material.

17. A memory device, comprising:
a resistive memory material;
a word line (WL);
a bit line (BL) coupled to the WL across the resistive memory material; and
circuitry configured to:
activate the memory device by floating the BL and applying a WL read bias voltage (WLV); and
deliver a repair current by recoupling the BL to a BL read bias voltage (BLV).

18. The memory device of claim 17 , wherein the circuitry comprises:
a BL select switch coupled between the BLV and the BL, the BL select switch operable to gate coupling of the BLV to the BL; and
a control input coupled to the BL select switch to operate the BL select switch.

19. The memory device of claim 17 , further comprising:
a plurality of resistive memory elements arranged in an array;
a plurality of WLs coupled to groups of resistive memory elements across the array;
a plurality of BLs coupled to groups of resistive memory elements across the array, such that each resistive memory element is addressed in the array by a unique combination of a WL and a BL; and
a controller coupled to the plurality of WLs and the plurality of BLs to address the plurality of resistive memory elements in the array.

20. The memory device of claim 17 , the resistive memory material comprises phase change memory material.

Assignees

• Intel Corp

Inventors

• Mantegazza Davide
• Guliani Sandeep
• Srinivasan Balaji
• Pangal Kiran

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title