Method, apparatus and system for a per-DRAM addressability mode

Patent metadata

Field	Value
Publication number	US-10902890-B2
Application number	US-201213531368-A
Country	US
Kind code	B2
Filing date	Jun 22, 2012
Priority date	Jun 22, 2012
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Techniques and mechanisms for programming an operation mode of a dynamic random access memory (DRAM) device. In an embodiment, a memory controller stores a value in a mode register of a DRAM device, the value specifying whether a per-DRAM addressability (PDA) mode of the DRAM device is enabled. An external contact of the DRAM device is coupled to the memory controller device via a signal line of a data bus. In another embodiment, the memory controller sends a signal to the external contact while the PDA mode of the DRAM device is enabled, the signal to specify whether one or more features of the DRAM device are programmable.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) device comprising:
a memory array;
an external contact to couple the DRAM device to a signal line DQ0 of a data bus;
a mode register to store a value to indicate whether a per-DRAM addressability (PDA) mode of the DRAM device is enabled, the PDA mode to indicate that only selected DRAMs of a rank of multiple DRAMs are to process a command to make changes to a configuration setting, wherein the rank of multiple DRAMs includes the multiple DRAMs in parallel which all execute memory access commands in parallel when PDA mode is not enabled, wherein as a condition to a change of the value to enable the PDA mode the DRAM device is to perform write leveling; and
control logic coupled to the mode register, wherein, while the PDA mode of the DRAM device is enabled, the control logic is to condition programmability of one or more features of the DRAM device upon detection of a signal received via DQ0, including to select between execution of a received command and forego execution of the received command based on a logic value of the signal received via DQ0, wherein the control logic is to sample DQ0 during a sequence of a burst of data strobe signals to determine the logic value, wherein the sample is to be after a first rising edge of the burst of data strobe signals, on either a first falling edge or on a second rising edge of the burst of data strobe signals.

2. The DRAM device of claim 1 , wherein the DRAM device includes a DDR4 SDRAM device.

3. The DRAM device of claim 1 , wherein the DRAM device includes a LPDDR4 SDRAM device.

4. The DRAM device of claim 1 , wherein the programmability of the one or more features includes a programmability of an on-die termination parameter.

5. The DRAM device of claim 1 , wherein the programmability of the one or more features includes a programmability of a voltage reference parameter.

6. The DRAM device of claim 1 , wherein dynamic ODT is not supported when the DRAM device is in the PDA mode, and wherein the control logic to condition programmability of the one or more features further includes the control logic to assert on-die termination as a condition to sample the signal line.

7. A memory controller device comprising:
a data interface to couple the memory controller device via a signal line DQ0 of a data bus to an external contact of a dynamic random access memory (DRAM) device; and
memory access logic to store in a mode register of the DRAM device a value to indicate whether a per-DRAM addressability (PDA) mode of the DRAM device is enabled and to trigger the DRAM device to perform write leveling as a condition to store the value to enable the PDA mode, the PDA mode to indicate that only selected DRAMs of a rank of multiple DRAMs are to process a command to make changes to a configuration setting, wherein the rank of multiple DRAMs includes the multiple DRAMs in parallel which all execute memory access commands in parallel when PDA mode is not enabled, the memory access logic further to send a signal via DQ0 while the PDA mode of the DRAM device is enabled, the signal to specify whether one or more features of the DRAM device are programmable, wherein the signal causes the DRAM to select between execution of a command sent from the memory controller and forego execution of the command based on a logic value of the signal sent via DQ0, wherein the DRAM is to sample DQ0 during a sequence of a burst of data strobe signals to determine the logic value, wherein the sample is to be after a first rising edge of the burst of data strobe signals, on either a first falling edge or on a second rising edge of the burst of data strobe signals.

8. The memory controller device of claim 7 , wherein, while the PDA mode of the DRAM device is enabled, the memory access logic further to provide device-specific programming of an on-die termination parameter of the DRAM device.

9. The memory controller device of claim 7 , wherein, while the PDA mode of the DRAM device is enabled, the memory access logic further to provide device-specific programming of a voltage reference parameter of the DRAM device.

10. The memory controller device of claim 7 , wherein the DRAM device includes a DDR4 SDRAM device.

11. The memory controller device of claim 7 , wherein the DRAM device includes a LPDDR4 SDRAM device.

12. The memory controller device of claim 7 , wherein the memory controller is integrated in an integrated circuit with a processor.

13. The memory controller device of claim 7 , wherein dynamic ODT is not supported when the DRAM device is in the PDA mode, and wherein the memory access logic is further to assert on-die termination at the memory device as a condition to send the signal.

14. A method at a memory controller device, the method comprising:
storing a value in a mode register of a dynamic random access memory (DRAM) device, the value specifying whether a per-DRAM addressability (PDA) mode of the DRAM device is enabled, wherein an external contact of the DRAM device is coupled to the memory controller device via a signal line DQ0 of a data bus, the PDA mode indicating that only selected DRAMs of a rank of multiple DRAMs are to process a command to make changes to a configuration setting, wherein the rank of multiple DRAMs includes the multiple DRAMs in parallel which all execute memory access commands in parallel when PDA mode is not enabled;
triggering the DRAM device to perform write leveling as a condition to storing the value to enable the PDA mode; and
sending a signal via DQ0 while the PDA mode of the DRAM device is enabled, the signal to specify whether one or more features of the DRAM device are programmable, wherein sending the signal causes the DRAM to select between executing a subsequent command sent from the memory controller and foregoing execution of the command based on a logic value of the signal received via DQ0, wherein the DRAM is to sample DQ0 during a sequence of a burst of data strobe signals to determine the logic value, wherein the sample is to be after a first rising edge of the burst of data strobe signals, on either a first falling edge or on a second rising edge of the burst of data strobe signals.

15. The method of claim 14 , further comprising:
while the PDA mode of the DRAM device is enabled, providing device-specific programming of an on-die termination parameter of the DRAM device.

16. The method of claim 14 , further comprising:
while the PDA mode of the DRAM device is enabled, providing device-specific programming of a voltage reference parameter of the DRAM device.

17. The method of claim 14 , wherein the DRAM device includes a DDR4 SDRAM device.

18. The method of claim 14 , wherein the DRAM device includes a LPDDR4 SDRAM device.

19. The method of claim 14 , wherein the memory controller is integrated in an integrated circuit with a processor.

20. The method of claim 14 , wherein dynamic ODT is not supported when the DRAM device is in the PDA mode, and further comprising:
asserting on-die termination at the memory device as a condition to sending the signal.

21. A system comprising:
a data bus;
dynamic random access memory (DRAM) device including:
a memory array;
an external contact to couple the DRAM device to a signal line DQ0 of the data bus;
a mode register; and
control logic coupled to the mode register, wherein, while a per-DRAM addressability (PDA) mode of the DRAM device is enabled, wherein the DRAM device is to perform write leveling as a condition to enable t

Assignees

• Bains Kuljit S
• Intel Corp

Inventors

• Bains Kuljit S

Classifications

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4063 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title