Array substrate gate driving unit and apparatus thereof, driving method and display apparatus

Patent metadata

Field	Value
Publication number	US-10902810-B2
Application number	US-201715751066-A
Country	US
Kind code	B2
Filing date	Jul 28, 2017
Priority date	Jan 3, 2017
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

The present disclosure relates to an array substrate gate driving unit and an apparatus thereof, a driving method and a display apparatus. The array substrate gate driving unit includes: an input circuit, connected with an input signal terminal and a pull-up node PU; a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU; a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD; an output circuit, connected with a clock signal terminal CLK, a second voltage signal terminal and a control circuit; a reset circuit, connected with a reset signal terminal Reset, the first voltage signal terminal and the pull-up node PU; and the control circuit, connected with the pull-up node PU and the output circuit.

First claim

What is claimed is:

1. A gate driver on array (GOA) unit, comprising:
an input circuit, connected with an input signal terminal and a pull-up node PU;
a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU;
a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD;
an output circuit, connected with a clock signal terminal, a second voltage signal terminal and a control circuit;
a reset circuit, connected with a reset signal terminal, the first voltage signal terminal and the pull-up node PU; and
the control circuit, connected with the pull-up node PU and the output circuit,
wherein the input circuit controls a potential of the pull-up node PU in response to a received input signal;
the output circuit generates an output signal in response to a clock signal input to the output circuit and the potential of the pull-up node PU;
the control circuit disconnects the control circuit from the pull-up node PU in response to the output signal generated by the output circuit;
the output circuit comprises a first output transistor and a second output transistor, drain electrodes of the first output transistor and the second output transistor are connected with the clock signal terminal, a source electrode of the first output transistor is connected with an output terminal of the output circuit;
the control circuit comprises an inverter and a control switching element;
the control switching element comprises a first transistor, a drain electrode of the first transistor is connected with gate electrodes of the first output transistor and the second output transistor, and a source electrode of the first transistor is connected with the input circuit, the reset circuit and the pull-down circuit via the pull-up node PU;
the inverter comprises a second transistor and a third transistor, a gate electrode and a drain electrode of the second transistor are connected with a third voltage signal terminal, and a source electrode of the second transistor is connected with the gate electrode of the first transistor and a drain electrode of the third transistor; and
a source electrode of the second output transistor is connected with the gate electrode of the third transistor.

2. The GOA unit according to claim 1 , wherein:
the inverter further comprises a fourth transistor, the drain electrode of the second transistor and a gate electrode and a drain electrode of the fourth transistor are connected with the third voltage signal terminal, and a gate electrode of the second transistor is connected with a source electrode of the fourth transistor.

3. The GOA unit according to claim 1 , wherein a source electrode of the third transistor is connected with the first voltage signal terminal.

4. The GOA unit according to claim 1 , wherein resistance of the second transistor is greater than resistance of the third transistor.

5. The GOA unit according to claim 1 , wherein the clock signal, a first voltage signal, a second voltage signal and a third voltage signal are input to the GOA unit.

6. A driving method for a gate driver on array (GOA) unit, the GOA unit comprising:
an input circuit, connected with an input signal terminal and a pull-up node PU;
a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU;
a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD;
an output circuit, connected with a clock signal terminal, a second voltage signal terminal and a control circuit;
a reset circuit, connected with a reset signal terminal, the first voltage signal terminal and the pull-up node PU; and
the control circuit, connected with the pull-up node PU and the output circuit,
wherein the input circuit controls a potential of the pull-up node PU in response to a received input signal;
the output circuit generates an output signal in response to a clock signal input to the output circuit and the potential of the pull-up node PU;
the control circuit disconnects the control circuit from the pull-up node PU in response to the output signal generated by the output circuit;
the output circuit comprises a first output transistor and a second output transistor, drain electrodes of the first output transistor and the second output transistor are connected with the clock signal terminal, a source electrode of the first output transistor is connected with an output terminal of the output circuit;
the control circuit comprises an inverter and a control switching element;
the control switching element comprises a first transistor, a drain electrode of the first transistor is connected with gate electrodes of the first output transistor and the second output transistor, and a source electrode of the first transistor is connected with the input circuit, the reset circuit and the pull-down circuit via the pull-up node PU;
the inverter comprises a second transistor and a third transistor, a gate electrode and a drain electrode of the second transistor are connected with a third voltage signal terminal, and a source electrode of the second transistor is connected with the gate electrode of the first transistor and a drain electrode of the third transistor; and
a source electrode of the second output transistor is connected with the gate electrode of the third transistor,
the driving method comprises:
controlling the potential of the pull-up node PU by the input circuit in response to the received input signal;
generating the output signal by the output circuit in response to the clock signal input to the output circuit and the potential of the pull-up node PU; and
disconnecting the control circuit from the pull-up node PU by the control circuit in response to the output signal generated by the output circuit.

7. The driving method for the GOA unit according to claim 6 , wherein:
the control circuit disconnects a source electrode of a first transistor included in the control circuit from the pull-up node PU in response to the output signal generated by the output circuit.

8. The driving method for the GOA unit according to claim 7 , further comprising:
the control circuit switches on the connection of the source electrode of the first transistor to the pull-up node PU in response to the clock signal input to the output circuit, after disconnecting the source electrode of the first transistor from the pull-up node PU.

9. A GOA apparatus, comprising a plurality of cascaded GOA units according to claim 1 .

10. The GOA apparatus according to claim 9 , wherein in the cascaded GOA units,
a signal input terminal of each GOA unit except for a first GOA unit and a last GOA unit is connected with an output terminal of a preceding GOA unit that is adjacent to the each GOA, and
a reset signal terminal of each GOA unit except for the first GOA unit and the last GOA unit is connected with an output terminal of a following GOA unit that is adjacent to the each GOA.

11. A display apparatus, comprising the GOA apparatus according to claim 9 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• Han Mingfu
• Shang Guangliang
• Yao Xing
• Han Seung Woo
• Kim Jiha
• Zheng Haoliang
• Yuan Lijun
• Wang Zhichong

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G3/3696 Primary

  Generation of voltages supplied to electrode drivers · CPC title