Two address translations from a single table look-aside buffer read

Patent metadata

Field	Value
Publication number	US-10901913-B2
Application number	US-201916251795-A
Country	US
Kind code	B2
Filing date	Jan 18, 2019
Priority date	Jul 15, 2013
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.

First claim

What is claimed is:

1. A data processing device comprising:
a processing core;
memory to store data elements; and
a streaming engine coupled to the memory and configured to recall from the memory a data stream having a plurality of data elements that includes a first data element and a second data element, wherein the streaming engine includes:
an address generator to generate:
a first virtual memory address corresponding to the first data element, the first virtual memory address having a first plurality of most significant bits (MSBs) and a first plurality of least significant bits (LSBs); and
a second virtual memory address corresponding to the second data element, the second virtual memory address having a second plurality of most significant bits (MSBs) and a second plurality of least significant bits (LSBs); and

an address translation unit including:
an address translation table to store a plurality of entries, each entry including a plurality of MSBs for a virtual memory address and a plurality of MSBs for a physical memory address;
a first comparator circuit to compare the first plurality of MSBs of the first virtual memory address to each entry of the address translation table to determine whether the plurality of MSBs for a virtual memory address of any entry is a match to the first plurality of MSBs of the first virtual memory address, and to output an entry select signal upon detection of a match;
a selection circuit to select, in response to the entry select signal, the entry of the address translation table in which the plurality of MSBs for a virtual memory address matches the first plurality of MSBs of the first virtual memory address and to output the plurality of MSBs for a physical memory address of the selected entry;
first concatenation circuitry to receive the plurality of MSBs for a physical memory address of the selected entry and to produce a first physical memory address that corresponds to the first virtual memory address in which the first physical memory address has a plurality of MSBs and a plurality of LSBs, wherein the plurality of MSBs of the first physical memory address is equal to the plurality of MSBs for a physical memory address of the selected entry and the plurality of LSBs of the first physical memory address is equal to the first plurality of LSBs of the first virtual memory address;
a second comparator circuit to compare the first plurality of MSBs of the first virtual memory address to the second plurality of MSBs of the second virtual memory address and to output a second address valid signal when the first plurality of MSBs of the first virtual memory address matches the second plurality of MSBs of the second virtual memory address; and
second concatenation circuitry to produce a second physical memory address that corresponds to the second virtual memory address in which the second physical memory address has a plurality of MSBs and a plurality of LSBs, wherein the plurality of MSBs of the second physical memory address is equal to the plurality of MSBs for a physical memory address of the selected entry and the plurality of LSBs of the second physical memory address is equal to the plurality of LSBs of the second virtual memory address;

wherein the streaming engine is configured to:
recall the first data element from the memory using the first physical memory address;
provide the first data element to the processing core;
recall the second data element from the memory using the second physical memory address; and
provide the second data element to the processing core.

2. The data processing device of claim 1 , wherein the first comparator circuit is configured to output a first address valid signal upon detection of the match, the first address valid signal indicating that the first physical memory address is valid.

3. The data processing device of claim 1 , wherein each entry of the address translation table further includes a permission field indicating whether a portion of memory corresponding to the entry is readable or writeable.

4. The data processing device of claim 3 , wherein the first comparator circuit is configured to only output the entry signal indicating detection of the match when the permission field of the entry of the address translation table in which the match is found indicates that the portion of memory corresponding to the entry is readable.

5. The data processing device of claim 1 , wherein the second address valid signal indicates that the second physical memory address is valid.

6. The data processing device of claim 1 , wherein the streaming engine is configured to recall the second data element from the memory using the second physical memory address and to provide the first data element to the processing core.

7. The data processing device of claim 1 , wherein, when the second comparator circuit determines that the first plurality of MSBs of the first virtual memory address and the second plurality of MSBs of the second virtual memory address do not match, the address translation unit is configured to:
use the first comparator circuit to compare the second plurality of MSBs of the second virtual memory address to each entry of the address translation table to determine whether the plurality of MSBs for a virtual memory address of any entry is a match to the second plurality of MSBs of the second virtual memory address, and to output the entry select signal upon detection of a match;
use the selection circuit to select, in response to the entry select signal, the entry of the address translation table in which the plurality of MSBs for a virtual memory address matches the second plurality of MSBs of the second virtual memory address and to output the plurality of MSBs for a physical memory address of the selected entry; and
use the first concatenation circuitry to receive the plurality of MSBs for a physical memory address of the selected entry and to produce a third physical memory address that corresponds to the second virtual memory address in which the third physical memory address has a plurality of MSBs and a plurality of LSBs, wherein the plurality of MSBs of the third physical memory address is equal to the plurality of MSBs for a physical memory address of the selected entry and the plurality of LSBs of the third physical memory address is equal to the second plurality of LSBs of the second virtual memory address;
wherein the streaming engine is configured to recall the second data element from the memory using the third physical memory address and to provide the first data element to the processing core.

8. The data processing device of claim 1 , wherein the memory is a level two cache memory.

9. The data processing device of claim 1 , wherein the processing core is a digital signal processing core.

10. The data processing device of claim 1 , wherein the processing core, the memory, and the streaming engine are arranged on a single integrated circuit die.

11. A device comprising:
a streaming engine configured to couple between a processor and a cache, wherein the streaming engine includes:
an address generator configured to generate a first virtual address and a second virtual address, wherein the first virtual address includes a first set of bits and a second set of bits, and the second virtual address includes a third set of bits and a fourth set of bits; and
an address translation buffer coupled to the address generator and configured to:
store a set of translation entries;
receive the first virtual address and the second virtual address;
compare the first set of bits of the first virtual address to the set of translation entries;
based on the first set of bits of the first virtua

Assignees

• Texas Instruments Inc

Inventors

• Zbiciak Joseph
• Tran Son H

Classifications

• H03H17/0664

  where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30018

  Bit or string instructions · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title