Systems and methods for mitigating faults in combinatory logic

Patent metadata

Field	Value
Publication number	US-10901836-B2
Application number	US-201716326336-A
Country	US
Kind code	B2
Filing date	Sep 15, 2017
Priority date	Sep 16, 2016
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Methods, systems, and apparatus for detecting single event effects. The system includes a first-modulus digital logic unit and a second-modulus digital logic unit each configured to reduce one or more operands by a respective modulus, apply an arithmetic compute logic to the reduced operands to produce a respective compute output, and reduce the respective compute output by their respective modulus. The system includes a kernel digital logic unit configured to apply the arithmetic compute logic to the operands to produce a kernel compute output, output the kernel compute output reduced by the first modulus, and output the kernel compute output reduced by the second modulus. The system includes a detector configured to detect a single event effect based on the reduced first compute output, the kernel compute output reduced by the first modulus, the reduced second compute output, and the kernel compute output reduced by the second modulus.

First claim

What is claimed is:

1. A system for detecting single event effects, the system comprising:
a data input configured to provide one or more operands;
a first-modulus processor connected to the data input, and configured to:
reduce each of the one or more operands by a first modulus,
apply an arithmetic compute logic to the reduced one or more operands to produce a first compute output, and
reduce the first compute output by the first modulus;

a second-modulus processor connected to the data input and configured to:
reduce each of the one or more operands by a second modulus,
apply the arithmetic compute logic to the reduced one or more operands to produce a second compute output, and
reduce the second compute output by the second modulus;

a kernel processor connected to the data input, and configured to:
apply the arithmetic compute logic to the one or more operands to produce a kernel compute output,
output the kernel compute output reduced by the first modulus, and
output the kernel compute output reduced by the second modulus; and

a detector connected to the first-modulus processor, the second-modulus processor, and the kernel processor, the detector configured to:
receive, from the first-modulus processor, the reduced first compute output,
receive, from the second-modulus processor, the reduced second compute output,
receive, from the kernel processor, the kernel compute output reduced by the first modulus and the kernel compute output reduced by the second modulus, and
detect a single event effect based on a comparison of the reduced first compute output and the kernel compute output reduced by the first modulus, and a comparison of the reduced second compute output and the kernel compute output reduced by the second modulus.

2. The system of claim 1 , wherein the first-modulus processor comprises:
a set of first-modulus input residue code generators configured to receive the one or more operands from the data input, and reduce the one or more operands by the first modulus,
a first compute kernel configured to receive the one or more operands reduced by the first modulus from the set of first-modulus input residue code generators, and apply the arithmetic compute logic to the received reduced one or more operands to produce the first compute output, and
a first-modulus output residue code generator configured to receive the first compute output from the first compute kernel, and reduce the first compute output by the first modulus.

3. The system of claim 2 , wherein the second-modulus processor comprises:
a set of second-modulus input residue code generators configured to receive the one or more operands from the data input, and reduce the one or more operands by the second modulus,
a second compute kernel configured to receive the one or more operands reduced by the second modulus from the set of second-modulus input residue code generators, and apply the arithmetic compute logic to the received reduced one or more operands to produce the second compute output, and
a second-modulus output residue code generator configured to receive the second compute output from the second compute kernel, and reduce the second compute output by the second modulus.

4. The system of claim 3 , wherein the first modulus m is selected such that the algebraic set representable by 2 m is larger than the algebraic set representable by the combined bits of the largest operand to the first compute kernel,
wherein the second modulus n is selected such that the algebraic set representable by the 2 n is larger than the algebraic set representable by the combined bits of the largest operand to the second compute kernel, and
wherein the first modulus m and the second modulus n are both coprime, whereby the greatest common divisor to both the first modulus m and the second modulus n is the integer 1.

5. The system of claim 4 , wherein the first compute kernel is a reduced set compute kernel configured to perform the arithmetic compute logic to an operand having a bit size of m-bits, and
wherein second compute kernel is a reduced set compute kernel configured to perform the arithmetic compute logic to an operand having a bit size of n-bits.

6. The system of claim 1 , wherein the kernel processor comprises:
a third compute kernel configured to receive the one or more operands from the data input, and apply the arithmetic compute logic to the received one or more operands to produce the kernel compute output,
a kernel-unit first-modulus output residue code generator configured to receive the kernel compute output, and reduce the kernel compute output by the first modulus, and
a kernel-unit second-modulus output residue code generator configured to receive the kernel compute output, and reduce the kernel compute output by the second modulus.

7. The system of claim 1 , wherein the detector comprises:
a first comparator configured to compare the reduced first compute output from the first-modulus processor and the kernel compute output reduced by the first modulus from the kernel processor, and
a second comparator configured to compare the reduced second compute output from the second-modulus processor and the kernel compute output reduced by the second modulus from the kernel processor.

8. The system of claim 1 , wherein the detector is further configured to detect a fault caused by the detected single event effect and determine a position of the detected fault within the kernel compute output, and
wherein the system further comprises:
an error syndrome identifier connected to the detector, and configured to generate correction instructions for correcting the detected fault within the kernel compute output, and

a bit inverter connected to the error syndrome identifier, and configured to correct the detected fault within the kernel compute output based on the correction instructions.

9. An apparatus for detecting single event effects, the apparatus comprising:
a data input configured to provide one or more operands;
a first-modulus processor connected to the data input, and configured to:
reduce each of the one or more operands by a first modulus,
apply an arithmetic compute logic to the reduced one or more operands to produce a first compute output, and
reduce the first compute output by the first modulus;

a second-modulus processor connected to the data input and configured to:
reduce each of the one or more operands by a second modulus,
apply the arithmetic compute logic to the reduced one or more operands to produce a second compute output, and
reduce the second compute output by the second modulus;

a kernel processor connected to the data input, and configured to:
apply the arithmetic compute logic to the one or more operands to produce a kernel compute output,
output the kernel compute output reduced by the first modulus, and
output the kernel compute output reduced by the second modulus; and

a detector connected to the first-modulus processor, the second-modulus processor, and the kernel processor, the detector configured to:
receive, from the first-modulus processor, the reduced first compute output,
receive, from the second-modulus processor, the reduced second compute output,
receive, from the kernel processor, the kernel compute output reduced by the first modulus and the kernel compute output reduced by second first modulus, and
detect a single event effect based on a comparison of the reduced first compute output and the kernel compute output reduced by the first modulus, and a comparison of the reduced second compute output and the kernel compute output reduced by the second modulus.

10. The apparatus of claim 9 , wherein the first-modulus proces

Assignees

• Univ Southern California

Inventors

• Sika Michel

Classifications

• G06F11/00 Primary

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title

• G06F11/1629

  Error detection by comparing the output of redundant processing systems · CPC title

• G06F11/1024

  Identification of the type of error · CPC title

• G06F11/104 Primary

  using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title