Power amplifier and temperature compensation method for the power amplifier

US10901447B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10901447-B2
Application numberUS-201916575513-A
CountryUS
Kind codeB2
Filing dateSep 19, 2019
Priority dateApr 23, 2019
Publication dateJan 26, 2021
Grant dateJan 26, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A power amplifier configured to amplify a received input signal, and the power amplifier includes a bias circuit and an output stage circuit. The bias circuit includes a reference voltage circuit and a bias generating circuit. The reference voltage circuit receives the first system voltage and provides a reference voltage according to a first system voltage, and the reference voltage changes as the temperature of the wafer changes. The bias generating circuit receives the second system voltage and the reference voltage, and generates an operating voltage. The output stage circuit is coupled to the bias circuit to receive the operating voltage and the driving current to receive and amplify the input signal. When a chip temperature is changed, the bias generating circuit changes the operating voltage according to the reference voltage, such that the driving current approaches a predetermined value as the chip temperature rises.

First claim

Opening claim text (preview).

What is claimed is: 1. A power amplifier, configured to amplify an input signal received thereby, comprising: a bias circuit including: a reference voltage circuit configured to receive a first system voltage, and providing a reference voltage according to the first system voltage, wherein the reference voltage changes as a chip temperature changes; and a bias generating circuit electrically coupled to the reference voltage circuit, configured to receive a second system voltage and the reference voltage, and generating an operating voltage; and an output stage circuit electrically coupled to the bias circuit, wherein the output stage circuit is configured to receive the operating voltage and a driving current to receive and amplify the input signal; wherein the bias generating circuit is configured to change the operating voltage according to the reference voltage in responsive to the chip temperature changes, such that the driving current approaches a predetermined value as the chip temperature rises. 2. The power amplifier according to claim 1 , wherein the bias generating circuit includes: a first transistor having a first end configured to receive the second system voltage, a second end coupled to the output stage circuit through a bias resistor, and a third end configured to receive the reference voltage through a first resistor. 3. The power amplifier according to claim 2 , wherein the reference voltage circuit includes a bandgap reference voltage circuit, including: a fourth transistor having a first end coupled to the first system voltage, a second end coupled to the first system voltage through a second resistor, and a third end coupled to a first node; a third resistor having one end coupled to the first node; a fourth resistor having one end coupled to the first node; a fifth transistor having a first end coupled to another end of the third resistor; a sixth transistor having a first end coupled to another end of the fourth resistor and a third end short-circuited to the first end of the sixth transistor and coupled to the first end of the fifth transistor; a current mirror circuit respectively coupled to the second end of the fifth transistor, a second end of the sixth transistor and a common end, including a plurality of seventh transistors, wherein the bandgap reference voltage circuit is configured to change the reference voltage output at the first node according to the chip temperature; an eighth transistor having a first end coupled to the first node and a third end coupled between another end of the third resistor and the first end of the fifth transistor; and a ninth transistor having a first end coupled to a second end of the eighth transistor, a second end coupled to the common end, and a third end short-circuited to the first end of the ninth transistor. 4. The power amplifier according to claim 3 , wherein the bias circuit further includes an auxiliary circuit electrically coupled to the bias generating circuit, configured to change a reference current, wherein the bias generating circuit is further configured to receive the second system voltage, the reference voltage, and the reference current and generate the operating voltage, wherein the auxiliary circuit is configured to cause the reference current changes as the chip temperature changes, and wherein the bias generating circuit is configured to change the operating voltage in accordance with the reference voltage and the reference current, such that the driving current approaches the predetermined value as the chip temperature rises. 5. The power amplifier according to claim 4 , wherein the auxiliary circuit includes: a tenth transistor having a first end configured to provide the reference current and a third end coupled to the third end of the sixth transistor; and a plurality of eleventh transistors each having a third end coupled to the current mirror circuit. 6. The power amplifier according to claim 5 , wherein the reference current is changed according to a ratio a number of the eleventh transistors to a number of the seventh transistors, and the chip temperature. 7. The power amplifier according to claim 2 , wherein the reference voltage circuit includes a bandgap reference voltage circuit, including: a first amplifier having a first input end coupled to the first system voltage through a fifth resistor, a second input end coupled to the first system voltage through a sixth resistor, and an output end coupled to a second node; a twelfth transistor having a first end coupled to the first input end of the first amplifier, a second end coupled to a seventh resistor, and a third end coupled to a third node; a thirteenth transistor having a first end coupled to the second input end of the first amplifier, a second end coupled to another end of the seventh resistor, and a third end coupled to the third node; an eighth resistor coupled to the another end of the seventh resistor and a third system voltage; a ninth resistor coupled between the second node and the third node; and a tenth resistor coupled between the third node and the third system voltage, wherein the bandgap reference voltage circuit is configured to change the reference voltage output at the second node in accordance with the chip temperature. 8. The power amplifier according to claim 7 , wherein the bias circuit further includes an auxiliary circuit electrically coupled to the bias generating circuit, and the auxiliary circuit includes: a fourteenth transistor having a first end coupled to the bias generating circuit and configured to output a reference current, a second end coupled to the third system voltage through an eleventh resistor, and a third end coupled to the third nodes, wherein the bias generating circuit is configured to receive the third system voltage, the reference voltage and the reference current and generate the operating voltage, and the auxiliary circuit is configured to cause the reference current changes as the chip temperature changes, and the bias generating circuit is configured to change the operating voltage in accordance with the reference voltage and the reference current, such that the driving current approaches the predetermined value as the chip temperature rises. 9. The power amplifier according to claim 8 , wherein a resistance of the eleventh resistor is twice of a resistance of the eighth resistor. 10. The power amplifier according to claim 2 , wherein the reference voltage circuit includes a bandgap reference voltage circuit, including: a second amplifier having a first input end coupled to the first system voltage through a twelfth resistor, a second input end coupled to the first system voltage through a thirteenth resistor, and an output end coupled to a fourth node; a fifteenth transistor having a first end coupled to the first input end of the second amplifier, a second end coupled to a common end, and a third end coupled to the first end of the fifteenth transistor; and a sixteenth transistor having a first end coupled to the second input end of the second amplifier through a fourteenth resistor, a second end coupled to the common end, and a third end coupled to the first end of the sixteenth transistor; wherein the bandgap reference voltage circuit is configured to change the reference voltage output at the fourth node according to the chip temperature. 11. The power amplifier according to claim 10 , wherein the bias circuit further includes an auxiliary circuit electrically coupled to the bias generating circuit, and the auxiliary circuit includes: a seventeenth transistor having a first end coupled to the bias generating circuit and configured to output a reference cur

Assignees

Inventors

Classifications

  • producing a current or voltage as a predetermined function of the temperature · CPC title

  • using bipolar transistors only · CPC title

  • G05F3/262Primary

    using field-effect transistors only · CPC title

  • G05F3/245Primary

    producing a voltage or current as a predetermined function of the temperature · CPC title

  • H03F3/21Primary

    with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title

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What does patent US10901447B2 cover?
A power amplifier configured to amplify a received input signal, and the power amplifier includes a bias circuit and an output stage circuit. The bias circuit includes a reference voltage circuit and a bias generating circuit. The reference voltage circuit receives the first system voltage and provides a reference voltage according to a first system voltage, and the reference voltage changes as…
Who is the assignee on this patent?
Richwave Technology Corp
What technology area does this patent fall under?
Primary CPC classification G05F3/262. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 26 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).