Techniques in ensuring functional safety (fusa) systems

Patent metadata

Field	Value
Publication number	US-10901035-B2
Application number	US-201916265833-A
Country	US
Kind code	B2
Filing date	Feb 1, 2019
Priority date	Feb 1, 2019
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for in-field safety tests on system-level and circuit-level, providing real-time and on-chip tests with respect to, including but not limited to, circuit reliability, power consumption, and system safety. The in-field safety tests may include implementing voltage droop monitors (VDMs) and signature collectors with authentication-enabled launching. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. An apparatus of an integrated circuit (IC) comprising:
voltage droop monitors (VDMs) to measure voltage values of respective cores in a computing unit of the IC, wherein the VDMs are respectively embedded in each of the cores;
an interconnection to couple VDMs to one another in a ring network; and
a master core that is one of the cores, the master core to:
acquire measured voltage values from the VDMs;
determine individual functionalities of the respective cores to be functional or nonfunctional, based on comparison between the measured voltage values and at least one expected voltage value; and
determine, based on the determined functionalities, a status of the IC.

2. The apparatus of claim 1 , wherein each measured voltage value of the measured voltage values is associated with an operating frequency at which the corresponding core operates during the measurement, and the at least one expected voltage value is associated with the same operating frequency.

3. The apparatus of claim 1 , wherein the status of the IC is no error, non-critical error, or critical error.

4. The apparatus of claim 3 , wherein the master core is further to determine, based on the determined status of the IC, an operation to the IC, wherein the operation to the IC is to do nothing according to the status of no error, disable nonfunctional cores of the IC according to the status of non-critical error, or shut down the IC according to the status of critical error.

5. The apparatus of claim 1 , further comprising a security engine, wherein the master core is further to report the determined status of the IC to the security engine.

6. The apparatus of claim 5 , wherein the security engine is further to determine, based on the reported status of the IC, an operation to the IC, wherein the operation to the IC is to do nothing according to a status of no errors, disable nonfunctional cores of the IC according to a status of non-critical errors, or shut down the IC according to a status of critical errors.

7. The apparatus of claim 5 , wherein the security engine is further to report the determined status of the IC to a system controller to determine an operation to the IC.

8. The apparatus of claim 1 , wherein the VDMs are further to measure current values respectively corresponding to the measured voltage values of the cores to derive respective power values of the cores, or to measure power values of the cores.

9. The apparatus of claim 1 , wherein the VDMs are further to detect voltage droops, based on comparison between the measured voltage values and at least one expected voltage value that are predetermined.

10. The apparatus of claim 1 , further comprising VDMs that are embedded in other components on the IC to respectively detect voltage values of the other components, wherein the other components include an input/output (IO) port, a memory fabric, and a memory controller.

11. The apparatus of claim 10 , further comprising the IO port, to:
acquire the measured voltage values from the VDMs;
determine functionalities of the cores and the other components to be functional or nonfunctional, based on comparison between the measured voltage values and at least one expected voltage value;
determine, based on the determined functionalities, a status of the IC; and
determine, based on the determined status of the IC, an operation to the IC.

12. The apparatus of claim 11 , further comprising a logic controller to:
compare the functionalities determined by the master core and the functionalities determined by the IO port; and
determine the status of the IC based on the functionalities determination by the IO port.

13. One or more non-transitory computer-readable media (NTCRM) comprising instructions to, upon execution of the instructions by circuitry of an integrated circuit (IC), cause the IC to:
initiate a safety test program;
authenticate, by a security engine of a fabric launcher, the safety test program;
measure, by voltage droop monitors (VDMs), voltage droops of cores of the IC, wherein the VDMs are respectively embedded in each of the cores, and wherein the VDMs are coupled to one another in a ring network;
determine, by a master core that is one of the cores of the IC, respective functionalities of the cores to be functional or nonfunctional based on comparisons between the measured voltage droops and at least one threshold value;
determine, by the master core based on the determined functionalities, a status of the IC; and
determine, by the master core based on the determined status of the IC, an operation of the IC.

14. The NTCRM of claim 13 , wherein the status of the IC is no errors, non-critical errors, or critical errors.

15. The NTCRM of claim 13 , wherein, upon execution, the instructions are further to cause the IC to:
process, by the master core, the measured voltage droops from the VDMs;
process, by an IO port, the measured voltage droops from the VDMs;
determine the processed voltage droops by the master core are different from the processed voltage droops by the IO port; and
determine the respective functionalities of the cores to be functional or nonfunctional based on comparisons between processed voltage values by the IO port and at least one threshold value.

16. The NTCRM of claim 13 , wherein, upon execution, the instructions are further to cause the IC to:
generate signature data for a signature test;
acquire the signature test data transmitted to or from the cores of the IC;
compress the acquired data with a predetermined polynomial function to generate respective compressed values corresponding to the acquired data;
determine respective correctnesses of safety test program execution regarding the cores, based on comparison between the respective compressed values and one or more predetermined values; and
determine individual defectivenesses of the cores, based on the respective correctnesses by processing the signature data by the cores.

17. The NTCRM of claim 16 , wherein the instructions, upon execution, further cause the IC to determine operations to the IC, based on the determined functionalities and the defectivenesses of the cores of the IC.

Assignees

• Intel Corp

Inventors

• Pappu Lakshminarayana
• Srivastava Amit Kumar
• Milstrey Robert

Classifications

• G06F11/27

  Built-in tests · CPC title

• G06F11/26

  Functional testing · CPC title

• G01R31/31703

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title

• G06F11/30

  Monitoring · CPC title

• G01R31/2853

  Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66) · CPC title