Digital duty-cycle monitoring of a periodic signal

Patent metadata

Field	Value
Publication number	US-10901020-B2
Application number	US-201816118280-A
Country	US
Kind code	B2
Filing date	Aug 30, 2018
Priority date	Aug 30, 2018
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.

First claim

The invention claimed is:

1. A system comprising a duty-cycle-monitoring circuit configured to receive, from a signal-generating module, a monitored signal having cycles that have a high portion and a low portion, wherein:
the duty-cycle-monitoring circuit comprises:
a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal;
a plurality of corresponding flip-flops, wherein:
each flip-flop is triggered by a second signal based on the monitored signal; and
the data input of each flip-flop is connected to an output of a corresponding buffer; and

a control circuit configured to:
determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal; and
determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.

2. The system of claim 1 , wherein the control circuit is further configured to use the measures of the durations of the high and low portions to determine whether a duty cycle of the monitored signal has an expected value.

3. The system of claim 2 , wherein using the measures of the durations of the high and low portions to determine whether the duty cycle of the monitored signal has an expected value comprises comparing the measures of the durations of the high and low portions to determine whether they are equivalent.

4. The system of claim 1 , wherein each flip-flop of the plurality of flip-flops is a dual-edge-triggered flip-flop.

5. The system of claim 1 , wherein:
the measure of the duration of the high portion is based on the outputs of the plurality of flip-flops at a downtick of the second signal; and
the measure of the duration of the low portion is based on the outputs of the plurality of flip-flops at an uptick of the second signal.

6. The system of claim 5 wherein the second signal is identical to the monitored signal.

7. The system of claim 5 , wherein:
each flip-flop has a Q output;
the Q outputs of the flip-flops, at a downtick of the second signal, define a first thermometric code; and
the measure of the high portion of the cycle of the monitored signal is based on the first thermometric code.

8. The system of claim 7 , wherein:
the first signal corresponds to an inverse of the monitored cycle for the low portion of a first cycle of the monitored signal;
the Q outputs of the flip-flops, at an uptick of the second signal corresponding to the end of the low portion of the first cycle, define a second thermometric code; and
the measure of the duration of the low portion of the first cycle of the monitored signal is based on the second thermometric code.

9. The system of claim 7 , wherein:
each flip-flop has a ˜Q output;
the ˜Q outputs of the flip-flops, at an uptick of the second signal, define a second thermometric code; and
the measure of the duration of the low portion of the cycle of the monitored signal is based on the second thermometric code.

10. The system of claim 1 , wherein the first and second signals correspond to the monitored signal such that the monitored signal is provided to the first buffer and each flip-flop is triggered by the monitored signal.

11. The system of claim 1 , wherein:
the duty-cycle-monitoring circuit further comprises a clock/data module that receives the monitored signal and outputs the first signal and the second signal.

12. The system of claim 11 , wherein:
the clock/data module comprises a logic circuit and gating circuit;
the monitored signal is provided as an input to each of the logic circuit and the gating circuit;
the logic circuit controls the gating circuit to output the first signal such that the first signal is the inverse of the monitored signal for the low portion of a cycle of the monitored signal.

13. The system of claim 12 , wherein:
the logic circuit comprises a first, second, third, and fourth flip-flop;
the data input of each flip-flop receives an inverse of the output of the flip-flop;
the first flip-flop is triggered by the monitored signal;
the second flip-flop is triggered by the output of the first flip-flop;
the third flip-flop is triggered by an inverse of the monitored signal;
the fourth flip-flop is triggered the output of the third flip-flop;
the outputs of the flip-flops define a digital code for controlling the gating circuit.

14. The system of claim 1 , wherein:
the plurality of flip-flops comprises N flip-flops;
the control circuit comprise an N:M encoder and a controller;
the encoder receives the outputs of the N flip-flops corresponding to the measures of the durations of the high and low portions;
the encoder encodes the outputs into M-bit codes corresponding to the measures of the durations of the high and low portions, where N>M;
the encoder provides the M-bit codes to the controller;
the controller is configured to use the M-bit codes to determine whether a duty cycle of the monitored signal has an expected value.

15. The system of claim 1 , wherein the system is an Advanced Driver Assistance System (ADAS).

16. A method for a system comprising a duty-cycle-monitoring circuit, the method comprising:
receiving, by the duty-cycle-monitoring circuit, from a signal-generating module, a monitored signal having cycles that have a high portion and a low portion;
providing a first signal based on the monitored signal to a first buffer of a cascade of buffers;
providing a second signal based on the monitored signal to each of a plurality of flip-flops corresponding to the cascade of buffers, wherein:
each flip-flop is triggered by the second signal; and
the data input of each flip-flop is connected to the output of a corresponding buffer;

determining, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal; and
determining, based on a state of the plurality of flip-flops, a measure of the duration of the low portion of a cycle of the monitored signal.

17. The method of claim 16 , further comprising using the measures of the durations of the high and low portions to determine whether a duty cycle of the monitored signal has an expected value.

18. The method of claim 17 , wherein using the measures of the durations of the high and low portions to determine whether the duty cycle of the monitored signal has an expected value comprises comparing the measures of the durations of the high and low portions to determine whether they are equivalent.

19. The method of claim 16 , wherein:
the measure of the duration of the high portion is based on the outputs of the plurality of flip-flops at a downtick of the second signal; and
the measure of the duration of the low portion is based on the outputs of the plurality of flip-flops at an uptick of the second signal.

20. The method of claim 19 wherein the second signal is identical to the monitored signal.

21. The method of claim 19 , wherein:
each flip-flop has a Q output;
the Q outputs of the flip-flops, at a downtick of the second signal, define a first thermometric code; and
the measure of the duration of the high portion of the cycle of the monitored signal is based on the first thermometric code.

22. The method of claim 21 , wherein:
the first signal corresponds to an inverse of the monitored cycle for the low portion of a first cycle of the monitored signal;
the Q

Assignees

• Qualcomm Inc

Inventors

• Jain Palkesh
• Gulati Rahul
• Meisarosh Edward Jacob

Classifications

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R29/02 Primary

  Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration · CPC title

• G01R29/0273 Primary

  the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit) · CPC title