Multi-level capacitive digital-to-analog converter for use in a sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-10897232-B2
Application number	US-201816614957-A
Country	US
Kind code	B2
Filing date	Apr 18, 2018
Priority date	May 24, 2017
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

A multi-level capacitive digital-to-analog converter, comprises at least one capacitor switch circuit ( 100 ) including a differential operational amplifier ( 130 ) having a first input node (E 130 a ) and a second input node (E 130 b ). A first current path ( 101 ) is coupled to a first reference input terminal (E 100 a ) to apply a first reference potential (RefP) and the second current path ( 102 ) is coupled to a second reference input terminal (E 100 b ) to apply a second reference potential (RefN). The at least one capacitor switch circuit ( 100 ) comprises a first controllable switch ( 111 ) being arranged between the second input node (E 130 a ) of the differential operational amplifier ( 130 ) and the first current path ( 101 ). The at least one capacitor switch circuit ( 100 ) comprises a second controllable switch ( 112 ) being arranged between the first input node (E 130 a ) of the differential operational amplifier ( 130 ) and the second current path ( 102 ).

First claim

The invention claimed is:

1. A multi-level capacitive digital-to-analog converter, comprising:
at least one capacitor switch circuit having a first reference input terminal to apply a first reference potential and a second reference input terminal to apply a second reference potential, wherein the at least one capacitor switch circuit comprises:
a differential operational amplifier having a first input node and a second input node,
a first current path and a second current path, the first current path being coupled to the first reference input terminal and the second current path being coupled to the second reference input terminal,
wherein the first input node of the differential operational amplifier is connected to the first current path and the second input node of the differential operational amplifier is connected to the second current path,

a first controllable switch being arranged between the second input node of the differential operational amplifier and the first current path,
a second controllable switch being arranged between the first input node of the differential operational amplifier and the second current path,
a first integrating capacitor and a second integrating capacitor,
a first transfer capacitor and a second transfer capacitor,
wherein the first transfer capacitor is arranged in the first current path between the first reference input terminal and the first integrating capacitor, and
wherein the second transfer capacitor is arranged in the second current path between the second reference input terminal and the second integrating capacitor,

a third controllable switch and a fourth controllable switch,
wherein the third controllable switch is arranged in the first current path between the first integrating capacitor and the first transfer capacitor, and
wherein the fourth controllable switch is arranged in the second current path between the second integrating capacitor and the second transfer capacitor, a fifth and a sixth controllable switch,
wherein the fifth controllable switch is arranged between a third reference potential and a first position of the first current path, said first position of the first current path being located between the third controllable switch and the first transfer capacitor,
wherein the sixth controllable switch is arranged between the third reference potential and a first position of the second current path, said first position of the second current path being located between the fourth controllable switch and the second transfer capacitor,
wherein the first controllable switch is arranged between the second input node of the differential operational amplifier and the first position of the first current path, and
wherein the second controllable switch is arranged between the first input node of the differential operational amplifier and the first position of the second current path,

a seventh controllable switch being arranged in the first current path between the first reference input terminal and the first transfer capacitor,
an eighth controllable switch being arranged in the second current path between the second reference input terminal and the second transfer capacitor,
a ninth controllable switch being arranged between the second reference input terminal and a second position of the first current path, said second position of the first current path being located between the seventh controllable switch and the first transfer capacitor,
a tenth controllable switch being arranged between the first reference input terminal and a second position of the second current path, said second position of the second current path being located between the eighth controllable switch and the second transfer capacitor,
an eleventh controllable switch being arranged between the third reference potential and the second position of the first current path, and
a twelfth controllable switch being arranged between the third reference potential and the second position of the second current path.

2. The multi-level capacitive digital-to-analog converter of claim 1 ,
wherein the at least one capacitor switch circuit comprises a first output terminal and a second output terminal to generate an output signal between the first and second output terminal,
wherein the differential operational amplifier comprises a first output node being connected to the first output terminal and a second output node being connected to the second output terminal,
wherein the first integrating capacitor is arranged between the first input node and the first output node of the differential operational amplifier, and
wherein the second integrating capacitor is arranged between the second input node and the second output node of the differential operational amplifier.

3. The multi-level capacitive digital-to-analog converter of claim 2 , wherein the at least one capacitor switch circuit is configured to generate 7 levels of the output signal.

4. The multi-level capacitive digital-to-analog converter of claim 2 , comprising:
a number N of the at least one capacitor switch circuit,
wherein the multi-level capacitive digital-to-analog converter is configured to generate 8*N−1 levels of the output signal.

5. The multi-level capacitive digital-to-analog converter of claim 1 , comprising:
a switching controller being configured to control one of a conductive switch state and a non-conductive switching state of the controllable switches by generating respective switching signals.

6. The multi-level capacitive digital-to-analog converter of claim 5 ,
wherein the switching controller is configured to generate the switching signals with a plurality of different signal sequences of a first signal level and a second signal level of the switching signals during a first operational phase and a second operational phase of the multi-level capacitive digital-to-analog converter.

7. The multi-level capacitive digital-to-analog converter of claim 6 ,
wherein the controllable switches are configured to be operated in the conductive state, when the respective switching signal has the first signal level, and
wherein the controllable switches are configured to be operated in the non-conductive state, when the respective switching signal has the second signal level.

8. A sigma delta modulator, comprising:
an input terminal to apply an analog input signal,
forward path comprising a summation block, a loop filter and a multi-bit quantizer,
a feedback path comprising a multi-level capacitive digital-to-analog converter of claim 1 ,
wherein the summation block has a first input node being connected to the input terminal and a second input node being connected to the feedback path.

Assignees

• Ams Ag

Inventors

• Horii Daisuke

Classifications

• H03M3/342 Primary

  by double sampling, e.g. correlated double sampling · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03F3/005 Primary

  using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence) · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title