Buck converter with power saving mode

Patent metadata

Field	Value
Publication number	US-10897199-B2
Application number	US-201916375345-A
Country	US
Kind code	B2
Filing date	Apr 4, 2019
Priority date	Apr 4, 2019
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

First claim

The invention claimed is:

1. An apparatus comprising:
a reactive step-down circuit;
a switching circuit supplying an input to the reactive step-down circuit and receiving a regulated voltage from the reactive step-down circuit, the switching circuit being configured to:
operate in an active mode configured to supply power in to the reactive step-down circuit according to the regulated voltage by evaluating the regulated voltage at a high frequency; and
operate in a sleep mode configured to supply power to the reactive step-down circuit by evaluating the regulated voltage at a low frequency that is less than the high frequency;

a comparator having a comparator output coupled to a gate of a transistor selectively coupling a drive voltage to the reactive step-down circuit and having comparator inputs coupled to a reference voltage and a function of the regulated voltage, the switching circuit being configured to poll the comparator at the high frequency in the active mode and to poi the comparator at the low frequency in the sleep mode; and
a high frequency clock outputting a first clock signal at the high frequency and a low frequency clock outputting a second clock signal at the low frequency;
wherein the switching circuit comprises a first multiplexer having:
a first multiplexer input coupled to the high frequency clock,
a second multiplexer input coupled to the low frequency clock,
a first select input coupled to a mode selector line, and

a first multiplexer output coupled to a clock input of the comparator, the first multiplexer configured to couple the high frequency clock to the first multiplexer output when the mode selector line indicates operation in the active mode.

2. The apparatus of claim 1 , wherein the reactive step-down circuit operates as a buck converter.

3. The apparatus of claim 1 , wherein the switching circuit further comprises: a second multiplexer having: a third multiplexer input coupled to the high frequency clock; a second select input coupled to the mode selector line; and a second multiplexer output, the second multiplexer configured to couple the high frequency clock to the second multiplexer output when the mode selector line indicates operation in the active mode; and a counter having a start input, a clock input, and a control output, wherein: the start input is coupled to the comparator output; the control output is coupled to the gate of the transistor; the clock input is coupled to the second multiplexer output; and the counter is configured to output a transition in the control output after counting a programmed number of cycles on the clock input occurring after detecting a transition on the start input.

4. The apparatus of claim 3 , further comprising a ring oscillator having an oscillator output coupled to a fourth multiplexer input of the seond multiplexer, the second multiplexer configured to couple the oscillator output to the clock input of the counter when the mode selector line indicates operation in the sleep mode.

5. The apparatus of claim 4 , wherein the ring oscillator is further configured to output a pulse train in response to a transition on the comparator output.

6. The apparatus of claim 3 , wherein the transistor is a PMOS (p-channel metal oxide semiconductor) transistor, the switching circuit further comprising an NMOS (n-channel metal oxide semiconductor) transistor selectively coupling a ground potential to the reactive step-down circuit; and
wherein the switching circuit further comprises a flip flop having a flip flop input coupled to the control output of the counter and a flip flop output coupled to a gate of the NMOS transistor.

7. The apparatus of claim 1 , wherein the switching circuit further comprises:
a feedback circuit configured to generate a feedback signal on a feedback output according to an evaluation of the regulated voltage with respect to a reference voltage, the feedback circuit having a component configured to operate at at least one of a lower voltage and a lower current in the sleep mode than in the active mode.

8. An apparatus comprising:
a reactive step-down circuit; and
a switching circuit supplying an input to the reactive step-down circuit and receiving a regulated voltage from the reactive step-down circuit, the switching circuit being configured to:
operate in an active mode configured to supply power in to the reactive step-down circuit according to the regulated voltage by evaluating the regulated voltage at a high fluency; and
operate in a sleep mode configured to supply power to the reactive step-down circuit by evaluating the regulated voltage at a low frequency that is less than the high frequency;

wherein the switching circuit further comprises a feedback circuit configured to generate a feedback signal on a feedback output according to an evaluation of the regulated voltage with respect to a reference voltage the feedback circuit having a component configured to operate at at least one of a lower voltage and a lower current in the sleep mode than in the active mode; and
wherein the feedback circuit comprises:
a comparator having a first comparator input coupled to the reference voltage, a second comparator input, and a comparator output, the comparator configured to output a high voltage on the comparator output when the first comparator input is at a higher voltage than the second comparator input;
a first voltage divider having a first divider input coupled to the regulated voltage and a first divider output; and
a second voltage divider having a second divider input coupled to the regulated voltage and a second divider output, wherein the second voltage divider has a higher impedance than the first voltage divider;
a multiplexer having a first multiplexer input coupled to the first divider output, a second multiplexer input coupled to the second divider output, a multiplexer output coupled to the second comparator input, and a select input coupled to a mode selection line, the multiplexer configured to couple the first multiplexer input to the multiplexer output when a signal on the mode selection line indicates operation in the active mode.

9. The apparatus of claim 8 , wherein the first voltage divider is a resistive divider and wherein the second voltage divider is a diode divider.

10. An apparatus comprising:
a reactive step-down circuit; and
a switching circuit supplying an input to the reactive step-down circuit and receiving a regulated voltage from the reactive step-down circuit, the switching circuit being configured to:
operate in an active mode configured to supply power in to the reactive step-down circuit according to the regulated voltage by evaluating the regulated voltage at a high frequency; and
operate in a sleep mode configured to supply power to the reactive step-down circuit by evaluating the regulated voltage at a low frequency that is less than the high frequency;

wherein the switching circuit further comprises a feedback circuit configured to generate a feedback signal on a feedback output according to an evaluation of the regulated voltage with respect to a reference voltage, the feedback circuit having a component configured to operate at at least one of a lower voltage and a lower current in the sleep mode than in the active mode; and
wherein the feedback circuit comprises:
a comparator having a first comparator input, a second comparator input, and a comparator output, the comparator configured to output a high voltage on the comparator output when the first comparator input is greater than the second comparator input, the comparator further including a bias current input;
a first current source;
a second current source having a smaller output current then t

Assignees

• Ambiq Micro Inc

Inventors

• Bogue Ivan
• Lu Yanning

Classifications

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title

• H02M1/0054

  Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035) · CPC title

• H02M1/0032

  Control circuits allowing low power mode operation, e.g. in standby mode · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• H02M1/0003

  Details of control, feedback or regulation circuits · CPC title