Memory including a selector switch on a variable resistance memory cell

Patent metadata

Field	Value
Publication number	US-10896930-B2
Application number	US-201916440596-A
Country	US
Kind code	B2
Filing date	Jun 13, 2019
Priority date	Nov 30, 2009
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A method comprising:
forming a sealing material on at least a sidewall of a selector switch and at least a sidewall of a memory cell, wherein the sealing material is formed after the memory cell and the selector switch; and
forming a conductive plug in contact with and disposed on at least a portion of a surface of the sealing material.

2. The method of claim 1 , further comprising:
forming the selector switch in contact with a portion of the memory cell.

3. The method of claim 2 , wherein forming the selector switch further comprises:
forming a first metal material; and
forming a first non-silicon-based semiconductor material in contact with an upper surface of the first metal material.

4. The method of claim 3 , wherein forming the selector switch further comprises:
forming a second metal material; and
forming a second non-silicon-based semiconductor material disposed between the first non-silicon-based semiconductor material and the second metal material.

5. The method of claim 4 , wherein the second non-silicon-based semiconductor material is in contact with the first non-silicon-based semiconductor material and with the second metal material.

6. The method of claim 1 , further comprising:
forming an upper electrode material and a lower electrode material; and
forming a variable resistance memory material disposed between the upper electrode material and the lower electrode material.

7. The method of claim 1 , further comprising:
forming a dielectric material in contact with at least a portion of the selector switch, wherein at least a portion of the dielectric material is in contact with at least a portion of the sealing material.

8. A memory array, comprising:
a plurality of memory cells that are each coupled with a corresponding bit line and a corresponding word line;
a plurality of selector switches that are each in contact with a corresponding memory cell of the plurality;
a sealing material in contact with a pair of sidewalls of each of the selector switches, an upper surface of each of the memory cells, and a pair of sidewalls of each of the memory cells; and
a plurality of conductive plugs that are each in contact with a corresponding memory cell of the plurality.

9. The memory array of claim 8 , wherein each selector switch of the plurality comprises a first metal material and a first non-silicon-based semiconductor material in contact with the first metal material.

10. The memory array of claim 9 , wherein each selector switch of the plurality comprises a second metal material and a second non-silicon-based semiconductor material disposed between the first non-silicon-based semiconductor material and the second metal material.

11. The memory array of claim 8 , wherein each conductive plug of the plurality is configured to pass electrical current between a corresponding selector switch and a corresponding word line.

12. The memory array of claim 8 , further comprising:
a second plurality of memory cells, each memory cell of the second plurality coupled with a corresponding second bit line and a corresponding second word line;
a second plurality of selector switches, each selector switch of the second plurality in contact with a corresponding memory cell of the second plurality;
a second sealing material in contact with a pair of sidewalls of each of the selector switches of the second plurality and a pair of sidewalls of each of the memory cells of the second plurality,
wherein each memory cell of the plurality is at a first level of the memory array and each memory cell of the second plurality is at a second level of the memory array.

13. The memory array of claim 8 , further comprising:
a plurality of second conductive plugs, each second conductive plug in contact with a corresponding memory cell of the second plurality, wherein the second conductive plugs are configured to pass electrical current between the corresponding memory cell of the second plurality and a corresponding second bit line.

14. A method for forming a memory device, comprising:
forming a sealing material on a pair of sidewalls of a selector switch and a pair of sidewalls of a memory cell, wherein the sealing material is formed after the memory cell and the selector switch; and
forming a conductive plug in contact with and disposed on at least a portion of a surface of the sealing material.

15. The method of claim 14 , further comprising:
forming the memory cell on at least a portion of the selector switch.

16. The method of claim 15 , wherein the memory cell is in contact with and disposed on the portion of the selector switch.

17. The method of claim 14 , wherein the conductive plug is in contact with the sealing material.

18. The method of claim 14 , further comprising:
forming a second conductive plug in contact with the selector switch.

19. The method of claim 18 , wherein the conductive plug comprises a first metal material and the second conductive plug comprises a second metal material different from the first metal material.

Assignees

• Micron Technology Inc

Inventors

• Redaelli Andrea
• Pirovano Agostino

Classifications

• H10K19/00

  Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 · CPC title

• H10B63/20

  comprising selection components having two electrodes, e.g. diodes · CPC title

• G11C13/00 Primary

  Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 · CPC title

• G11C13/0014

  comprising cells based on organic memory material · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title