Method, and storage medium and also device for carrying out same

Patent metadata

Field	Value
Publication number	US-10896281-B2
Application number	US-201916683725-A
Country	US
Kind code	B2
Filing date	Nov 14, 2019
Priority date	Nov 16, 2018
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

A method for the computer-aided characterization of a circuit comprising a semiconductor layer and a semiconductor component region embedded in the semiconductor layer in an electrically insulated manner, wherein the semiconductor component region is optionally coupled to a dielectric layer structure to be protected, the method comprising determining an indication representing vis-à-vis the semiconductor layer an intensity of an electrical charging of the semiconductor component region by a production process used to produce the circuit, wherein a physical construction of the semiconductor component region is taken into account when determining the indication, and classifying the semiconductor component region taking account of the indication.

First claim

What is claimed is:

1. A method for computer-aided characterization of a circuit comprising a semiconductor layer and a semiconductor component region embedded in the semiconductor layer in an electrically insulated manner, the method comprising:
obtaining a circuit model of the circuit;
using the circuit model, determining an indication representing an intensity of an electrical charging of the semiconductor component region by a production process used to produce the circuit with respect to the semiconductor layer, wherein a physical construction of the semiconductor component region is taken into account when determining the indication;
classifying the semiconductor component region taking account of the indication, including at least one electrical charging jeopardized classification in a first iteration of the method; and
adapting the circuit model to generate an adapted circuit model on the basis of a result of the classifying including the at least one electrical charging jeopardized classification.

2. The method as claimed in claim 1 ,
wherein a spatial surface area of the semiconductor component region is taken into account when determining the indication.

3. The method as claimed in claim 1 ,
wherein determining the indication comprises taking account of whether the semiconductor component region comprises a semiconductor junction.

4. The method as claimed in claim 1 ,
wherein the classifying comprises taking account of whether the semiconductor component region adjoins a dielectric layer structure to be protected.

5. The method as claimed in claim 1 ,
wherein the classifying comprises taking account of whether the semiconductor component region is electrically conductively coupled to an electrode structure, and
wherein the electrode structure and the semiconductor layer adjoin a dielectric layer structure to be protected, which is arranged at a distance from the semiconductor component region.

6. The method as claimed in claim 4 ,
wherein a physical construction of the dielectric layer structure to be protected is taken into account when determining the indication.

7. The method as claimed in claim 4 , further comprising:
determining a property of the dielectric layer structure, wherein the property of the dielectric layer structure represents an electrical breakdown strength of the dielectric layer structure,
wherein classifying the semiconductor component region is furthermore carried out taking account of the property of the dielectric layer structure.

8. The method as claimed in claim 4 ,
wherein classifying the semiconductor component region comprises taking account of whether the dielectric layer structure is physically contacted by a discharge path that is electrically insulated from the semiconductor component region.

9. The method as claimed in claim 8 , further comprising:
determining a property of the discharge path which represents an impedance of the discharge path,
wherein classifying the semiconductor component region is furthermore carried out taking account of the property of the discharge path.

10. The method as claimed in claim 4 , further comprising:
determining a property of the circuit which represents an interaction between the intensity of the electrical charging of the semiconductor component region and an electric field strength brought about thereby in the dielectric layer structure,
wherein classifying the semiconductor component region is furthermore carried out taking account of the property of the circuit.

11. The method as claimed in any of claim 4 , further comprising:
determining an interconnection of the dielectric layer structure in the circuit,
wherein classifying the semiconductor component region is furthermore carried out taking account of the interconnection of the dielectric layer structure.

12. The method as claimed in claim 4 ,
wherein classifying the semiconductor component region comprises taking account of whether the dielectric layer structure comprises a plurality of dielectric layers which are arranged at a distance from one another and are electrically coupled to one another.

13. The method as claimed in claim 12 ,
wherein classifying the semiconductor component region, for each layer of the dielectric layer structure, comprises taking account of whether the dielectric layer structure is part of a field effect component of the circuit.

14. The method as claimed in claim 1 , further comprising:
determining an electrically conductive path along which the electrical charging by the production process is coupled in; and
determining a property of the electrically conductive path which represents an impedance of the electrically conductive path,
wherein classifying the semiconductor component region is furthermore carried out taking account of the property of the electrically conductive path.

15. The method as claimed in claim 1 , further comprising:
determining a protective circuit structure, which is electrically coupled to the semiconductor component region,
wherein a property of the protective circuit structure and/or of the electrical coupling between the protective circuit structure and the semiconductor component region is taken into account when determining the indication.

16. The method as claimed in claim 15 ,
wherein the property of the protective circuit structure and/or of the electrical coupling comprises a physical construction, a capacitance, an impedance and/or a spatial position at the semiconductor component region.

17. The method as claimed in claim 1 ,
wherein determining the indication comprises taking account of whether the semiconductor component region comprises a plurality of segments which are arranged at a distance from one another and/or among one another are electrically conductively coupled to one another.

18. The method as claimed in claim 1 ,
wherein classifying the semiconductor component region comprises taking account of whether the semiconductor component region implements a logic circuit function.

19. The method as claimed in claim 1 , further comprising:
determining an additional indication representing a relationship between the physical construction of the semiconductor component region and a reference construction,
wherein classifying the semiconductor component region is furthermore carried out taking account of the additional indication.

20. The method as claimed in claim 19 , further comprising:
determining a plurality of protective circuit structures, which are electrically coupled to the semiconductor component region,
wherein a spatial distribution with which the plurality of protective circuit structures are coupled to the semiconductor component region is taken into account when determining the additional indication.

21. The method as claimed in claim 1 , further comprising:
determining a coupling between the semiconductor layer and the semiconductor component region; and
determining a capability of the coupling to counteract the electrical charging of the semiconductor component region with respect to the semiconductor layer,
wherein classifying the semiconductor component region is carried out taking account of the capability.

22. The method as claimed in claim 1 ,
wherein a network analysis of the circuit is carried out when determining the indication.

23. The method as claimed in claim 22 ,
wherein at least one electrical property of the circuit which represents an interaction o

Assignees

• Infineon Technologies Ag

Inventors

• Martin Andreas
• Beckmeier Daniel

Classifications

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F2111/20

  Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title