Informative value in indexing, classifying, searching

Patent metadata

Field	Value
Publication number	US-10896134-B2
Application number	US-201816233731-A
Country	US
Kind code	B2
Filing date	Dec 27, 2018
Priority date	Aug 22, 2018
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

A data processing system comprises a host that includes a first memory; and a memory system that includes a controller having a second memory, and a memory device, wherein the controller: checks whether a first mapping table whose mapping information is changed exists or not in a first list, checks whether a memory block corresponding to a piece of map data included in the first mapping table exists or not in a second list, and decides that the first mapping table is to be shortly updated due to an internal operation and does not transfer the first mapping table to the host when the memory block corresponding to the map data included in the first mapping table exists in the second list.

First claim

What is claimed is:

1. A method for operating a data processing system provided with a host including a first memory, a memory device, and a controller including a second memory, the method comprising:
checking, by the controller, whether a first mapping table whose mapping information is changed exists or not in a memory mapping table change list and then checking, by the controller, whether the first mapping table exists or not in the second memory;
checking, by the controller, whether a memory block corresponding to a piece of map data included in the first mapping table exists or not in a candidate block list, when the first mapping table exists in the second memory;
deciding, by the controller, that the first mapping table is to be updated due to an internal operation and returning to the checking, when the memory block corresponding to the map data exists in the candidate block list;
transferring, by the controller, the first mapping table to the host, when any memory block corresponding to any piece of map data does not exist in the candidate block list; and
receiving, by the host, the first mapping table from the controller and updating, by the host, a second mapping table included in the first memory and corresponding to the first mapping table,
wherein the memory mapping table change list includes the entry information for a mapping table including changed map data due to a command operation or an internal operation,
wherein the candidate block list includes information for the memory blocks for which an internal operation is to be performed among a plurality of blocks, and
wherein the internal operation may be any one among a garbage collection operation, a read reclaim operation and a wear leveling operation.

2. The method of claim 1 , wherein the receiving and updating includes:
providing, by the controller, entry information of the first mapping table along with a response to the host;
transferring, by the host, a read buffer command requesting the controller for the first mapping table;
transferring, by the controller, the first mapping table to the host; and
updating, by the host, the second mapping table based on the first mapping.

3. The method of claim 1 , further comprising loading, by the memory device, the first mapping table onto the second memory when the first mapping table does not exist in the second memory.

4. The method of claim 1 , wherein the entry information for the mapping table includes one among a mapping table number, type information of the map data, and size information of the map data and the like.

5. The method of claim 1 , further comprising: selecting, by the controller, memory blocks in which an internal operation including a garbage collection operation, a read re-claim operation or a wear leveling operation is to be performed among a plurality of memory blocks and including, by the controller, the selected memory blocks in the candidate block list.

6. The method of claim 5 , wherein the selecting and including includes deciding whether a valid page count a memory block is equal to or less than a threshold value, and including the memory block, whose valid page count is equal to or less than the threshold value, in the candidate block list.

7. The method of claim 5 , wherein the selecting and including includes deciding whether a read count of a memory block is equal to or greater than a threshold value, and including the memory block, whose read count is equal to or greater than the threshold value, in the candidate block list.

8. The method of claim 5 , wherein the selecting and including includes deciding whether an erase/write cycle count of a memory block is equal to or greater than a threshold value, and including the memory block, whose erase/write cycle count is equal to or greater than the threshold value, in the candidate block list.

9. A data processing system, comprising:
a host that includes a first memory; and
a memory system that includes a controller having a second memory, and a memory device,
wherein the controller:
checks whether a first mapping table whose mapping information is changed exists or not in a memory mapping table change list,
checks whether a memory block corresponding to a piece of map data included in the first mapping table exists or not in a candidate block list, and
decides that the first mapping table is to be updated due to an internal operation and does not transfer the first mapping table to the host when the memory block corresponding to the map data included in the first mapping table exists in the candidate block list,
wherein the memory mapping table change list includes the entry information for a mapping table including changed map data due to a command operation or an internal operation,
wherein the candidate block list includes information for the memory blocks for which an internal operation is to be performed among a plurality of blocks, and
wherein the internal operation may be any one among a garbage collection operation, a read reclaim operation and a wear leveling operation.

10. The data processing system of claim 9 , wherein the controller further transfers the first mapping table to the host, when the memory block corresponding to the map data does not exist in the candidate block list.

11. The data processing system of claim 10 , wherein the host updates a second mapping table included in the first memory and corresponding to the first mapping table based on the first mapping table transferred from the controller.

12. The data processing system of claim 9 ,
wherein the controller checks, before the checking of whether a memory block corresponding to the map data included in the first mapping table exists or not in the candidate block list, whether the first mapping table exists or not in the second memory, and
wherein the memory device loads, when the first mapping table does not exist in the second memory, the first mapping table onto the second memory.

13. The data processing system of claim 9 ,
wherein the entry information for the mapping table includes one among a mapping table number, type information of the map data, and size information of the map data and the like.

14. The data processing system of claim 9 , wherein the controller further selects memory blocks in which an internal operation including a garbage collection operation, a read re-claim operation or a wear leveling operation is to be performed among a plurality of memory blocks and includes the selected memory blocks in the candidate block list.

15. The data processing system of claim 14 , wherein the controller performs the selecting and including by deciding whether a valid page count a memory block is equal to or less than a threshold value, and including the memory block, whose valid page count is equal to or less than the threshold value, in the candidate block list.

16. The data processing system of claim 14 , wherein the controller performs the selecting and including by deciding whether a read count of a memory block is equal to or greater than a threshold value, and including the memory block, whose read count is equal to or greater than the threshold value, in the candidate block list.

17. The data processing system of claim 14 , wherein the controller performs the selecting and including by deciding whether an erase/write cycle count of a memory block is equal to or greater than a threshold value, and including the memory block, whose erase/write cycle count is equal to or greater than the threshold value, in the candidate block list.

18. A memory syst

Assignees

• Sk Hynix Inc

Inventors

• Byun Eu-Joon

Classifications

• G06F2212/7211

  Wear leveling · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F12/0292 Primary

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F12/0253

  Garbage collection, i.e. reclamation of unreferenced memory · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title