Timing control circuit and operation method thereof

US10895933B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10895933-B2
Application numberUS-201916352844-A
CountryUS
Kind codeB2
Filing dateMar 14, 2019
Priority dateMar 14, 2019
Publication dateJan 19, 2021
Grant dateJan 19, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A timing control circuit and an operation method thereof are provided. The timing control circuit includes a receiving circuit, a line memory, and a timing generating circuit. The receiving circuit receives a video packet stream from the outside and provides an external horizontal sync signal and a first data signal. The line memory temporarily stores the first data signal, and outputs a second data signal to a source driver according to an internal horizontal sync signal generated by the timing generating circuit. A video frame period of the second data signal includes a video display operation period and a touch detection period. A video display operation period is divided into a plurality of sub-periods. The timing generating circuit performs a synchronization operation in each of the sub-periods, so as to synchronize the timing of the internal horizontal sync signal with the timing of the external horizontal sync signal.

First claim

Opening claim text (preview).

What is claimed is: 1. A timing control circuit, comprising: a receiving circuit, configured to receive a video packet stream from the outside and provide an external vertical sync signal, an external horizontal sync signal and a first data signal according to the video packet stream; a line memory, coupled to the receiving circuit to temporarily store the first data signal, and configured to output a second data signal to a source driver according to an internal vertical sync signal and an internal horizontal sync signal, so as to drive at least one data line of a touch display panel, wherein a video frame period of the second data signal comprises a video display operation period and a touch detection period, and the video display operation period is divided into a plurality of sub-periods; and a timing generating circuit, coupled to the receiving circuit to receive the external vertical sync signal and the external horizontal sync signal, and configured to generate the internal vertical sync signal and the internal horizontal sync signal to the line memory and perform a synchronization operation during each of the sub-periods, so as to synchronize a timing of the internal horizontal sync signal with a timing of the external horizontal sync signal. 2. The timing control circuit according to claim 1 , wherein a video frame period of the first data signal comprises a video transmission period, and a sum of a time length of the video display operation period and a time length of the touch detection period is smaller than or equal to a time length of the video transmission period. 3. The timing control circuit according to claim 1 , wherein a cycle of the internal horizontal sync signal is smaller than a cycle of the external horizontal sync signal. 4. The timing control circuit according to claim 3 , wherein the video transmission period comprises M line periods, the video display operation period is divided into N sub-periods, the cycle of the external horizontal sync signal is T, the cycle of the internal horizontal sync signal is t, and the cycle t is {[(M/N)−p]/(M/N)}*T, wherein p is a real number. 5. The timing control circuit according to claim 1 , wherein all the sub-periods in one video frame period of the second data signal are continuous. 6. The timing control circuit according to claim 1 , wherein the timing generating circuit further controls a gate driver during the video display operation period, so as to drive at least one scan line of the touch display panel. 7. The timing control circuit according to claim 1 , wherein the timing generating circuit controls a touch circuit during the touch detection period, so as to drive at least one touch sensor of the touch display panel. 8. The timing control circuit according to claim 7 , wherein the touch circuit drives the at least one touch sensor in a doze mode during the touch detection period. 9. An operation method of a timing control circuit, comprising: receiving a video packet stream from the outside of the timing control circuit by a receiving circuit; providing an external vertical sync signal, an external horizontal sync signal and a first data signal according to the video packet stream by the receiving circuit; temporarily storing the first data signal by a line memory; outputting a second data signal to a source driver according to an internal vertical sync signal and an internal horizontal sync signal by the line memory, so as to drive at least one data line of a touch display panel, wherein a video frame period of the second data signal comprises a video display operation period and a touch detection period, and the video display operation period is divided into a plurality of sub-periods; generating the internal vertical sync signal and the internal horizontal sync signal to the line memory by a timing generating circuit; and performing a synchronization operation during each of the sub-periods by the timing generating circuit, so as to synchronize a timing of the internal horizontal sync signal with a timing of the external horizontal sync signal. 10. The operation method according to claim 9 , wherein a video frame period of the first data signal comprises a video transmission period, and a sum of a time length of the video display operation period and a time length of the touch detection period is smaller than or equal to a time length of the video transmission period. 11. The operation method according to claim 9 , wherein a cycle of the internal horizontal sync signal is smaller than a cycle of the external horizontal sync signal. 12. The operation method according to claim 11 , wherein the video transmission period comprises M line periods, the video display operation period is divided into N sub-periods, the cycle of the external horizontal sync signal is T, the cycle of the internal horizontal sync signal is t, and the cycle t is {[(M/N)−p]/(M/N)}*T, wherein p is a real number. 13. The operation method according to claim 9 , wherein all the sub-periods in one video frame period of the second data signal are continuous. 14. The operation method according to claim 9 , further comprising: controlling a gate driver by the timing generating circuit during the video display operation period, so as to drive at least one scan line of the touch display panel. 15. The operation method according to claim 9 , further comprising: controlling a touch circuit by the timing generating circuit during the touch detection period, so as to drive at least one touch sensor of the touch display panel. 16. The operation method according to claim 15 , wherein the at least one touch sensor is driven in a doze mode by the touch circuit during the touch detection period.

Assignees

Inventors

Classifications

  • Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally · CPC title

  • Aspects of interface with display user · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

  • for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

  • G06F3/0412Primary

    Digitisers structurally integrated in a display · CPC title

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What does patent US10895933B2 cover?
A timing control circuit and an operation method thereof are provided. The timing control circuit includes a receiving circuit, a line memory, and a timing generating circuit. The receiving circuit receives a video packet stream from the outside and provides an external horizontal sync signal and a first data signal. The line memory temporarily stores the first data signal, and outputs a second…
Who is the assignee on this patent?
Novatek Microelectronics Corp
What technology area does this patent fall under?
Primary CPC classification G06F3/0412. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 19 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).