System and method of monitoring a switching transistor

Patent metadata

Field	Value
Publication number	US-10895601-B2
Application number	US-201916409131-A
Country	US
Kind code	B2
Filing date	May 10, 2019
Priority date	May 10, 2019
Publication date	Jan 19, 2021
Grant date	Jan 19, 2021

Abstract

In accordance with an embodiment, a method includes using a monitoring circuit disposed on a monolithic integrated circuit to monitor an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit; using a time measuring circuit disposed on the monolithic integrated circuit to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, where the first drive signal is configured to cause a change of state of the first switching transistor; using an analysis circuit disposed on the monolithic integrated circuit to compare the measured first time delay with a first predetermined threshold to form a first comparison result; and indicating a first error condition based on the first comparison result.

First claim

What is claimed is:

1. A method comprising:
using a monitoring circuit disposed on a monolithic integrated circuit, monitoring an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit;
using a time measuring circuit disposed on the monolithic integrated circuit, measuring a first time delay between a first input edge transition of a first drive signal and the first output edge transition, wherein the first drive signal is configured to cause a change of state of the first switching transistor;
using an analysis circuit disposed on the monolithic integrated circuit, comparing the measured first time delay with a first predetermined threshold to form a first comparison result;
indicating a first error condition based on the first comparison result;
using the monitoring circuit, monitoring an output signal of a second switching transistor for a second output edge transition at the monitoring terminal;
using the time measuring circuit, measuring a second time delay between a second input edge transition of a second drive signal and the second output edge transition, wherein the second drive signal is configured to cause a change of state of the second switching transistor;
using the analysis circuit, comparing the measured second time delay with a second predetermined threshold to form a second comparison result; and
indicating a second error condition based on the second comparison result.

2. The method of claim 1 , further comprising:
using the time measuring circuit, measuring at least one of:
a third time delay between a third input edge transition of the first drive signal and the second output edge transition, wherein the third input edge transition occurs when the first drive signal is de-asserted;
a fourth time delay between a fourth input edge transition of the second drive signal and the first output edge transition, wherein the fourth input edge transition occurs when the second drive signal is de-asserted;
a fifth time delay between the fourth input edge transition and the first input edge transition; or
a sixth time delay between the third input edge transition and the second input edge transition.

3. The method of claim 1 , further comprising driving a control terminal of the first switching transistor based on the first drive signal using a first drive circuit disposed on the monolithic integrated circuit.

4. The method of claim 1 , further comprising providing a drive current to a motor via the first switching transistor.

5. The method of claim 1 , further comprising:
generating a pulse-width modulated signal; and
generating the first drive signal based on the pulse-width modulated signal.

6. The method of claim 1 , further comprising deactivating the first switching transistor in response to indicating the first error condition.

7. A method comprising:
using a monitoring circuit disposed on a monolithic integrated circuit, monitoring an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit;
using a time measuring circuit disposed on the monolithic integrated circuit, measuring a first time delay between a first input edge transition of a first drive signal and the first output edge transition, wherein the first drive signal is configured to cause a change of state of the first switching transistor;
using an analysis circuit disposed on the monolithic integrated circuit, comparing the measured first time delay with a first predetermined threshold to form a first comparison result;
indicating a first error condition based on the first comparison result; and
performing a power-up test comprising:
before measuring the first time delay:
deactivating the first switching transistor via a first drive circuit disposed on the monolithic integrated circuit, and
using a current source, applying a first current at the monitoring terminal.

8. The method of claim 7 , further comprising:
using the monitoring circuit, monitoring an output signal of a second switching transistor for a second output edge transition at the monitoring terminal;
using the time measuring circuit, measuring a second time delay between a second input edge transition of a second drive signal and the second output edge transition, wherein the second drive signal is configured to cause a change of state of the second switching transistor;
using the analysis circuit, comparing the measured second time delay with a second predetermined threshold to form a second comparison result; and
indicating a second error condition based on the second comparison result.

9. The method of claim 7 , wherein the current source is disposed on the monolithic integrated circuit.

10. An integrated circuit comprising:
a monitoring circuit having an input coupled to a monitoring terminal configured to be coupled to an output terminal of a first switching transistor, wherein the monitoring circuit is configured to monitor an output signal at the monitoring terminal for a first output edge transition;
a time measuring circuit coupled to the monitoring circuit, wherein the time measuring circuit is configured to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, and wherein the first drive signal is configured to cause a change of state of the first switching transistor; and
an analysis circuit coupled to the time measuring circuit and configured to compare the measured first time delay with a first predetermined threshold to form a first comparison result and to indicate a first error condition based on the first comparison result, wherein:
the monitoring terminal is further configured to be coupled to an output terminal of a second switching transistor,
the monitoring circuit is further configured to monitor the output signal at the monitoring terminal for a second output edge transition,
the time measuring circuit is further configured to measure a second time delay between a second input edge transition of a second drive signal and the second input edge transition, wherein the second drive signal is configured to cause a change of state of the second switching transistor, and
the analysis circuit is further configured to compare the measured second time delay with a second predetermined threshold to form a second comparison result and to indicate a second error condition based on the second comparison result.

11. The integrated circuit of claim 10 , further comprising a first drive circuit disposed on the integrated circuit, wherein the first drive circuit has an output coupled to a first drive terminal configured to be coupled to a control terminal of the first switching transistor, and the first drive circuit is configured to change the state of the first switching transistor based on the first drive signal.

12. The integrated circuit of claim 11 , further comprising control logic coupled to the analysis circuit and the first drive circuit, wherein the control logic is configured to deactivate the first switching transistor via the first drive circuit in response to the analysis circuit indicating the first error condition.

13. The integrated circuit of claim 10 , further comprising:
a first drive circuit disposed on the integrated circuit, wherein the first drive circuit has an output coupled to a first drive terminal configured to be coupled to a control terminal of the first switching transistor, and wherein the first drive circuit is configured to change the state of the first switching transistor based on the

Assignees

• Infineon Technologies Ag

Inventors

• Bogus Matthias
• Barrenscheen Jens
• Heiling Christian
• Koeppl Benno
• Zannoth Markus

Classifications

• G01R31/3277 Primary

  of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches · CPC title

• G01R31/2621

  for testing field effect transistors, i.e. FET's · CPC title

• G01R31/2617

  for measuring switching properties thereof · CPC title

• G01R31/54

  Testing for continuity · CPC title

• G01R31/52

  Testing for short-circuits, leakage current or ground faults · CPC title