Communication apparatus, communication method, program, and communication system

Patent metadata

Field	Value
Publication number	US-10892852-B2
Application number	US-201716094944-A
Country	US
Kind code	B2
Filing date	May 2, 2017
Priority date	May 18, 2016
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

A master includes a transmission and receiving unit that transmits and receives signals to and from a slave, and the transmission and receiving unit receives read data read out from the slave, and typically drives the second bit of a preamble transmitted/received subsequent to the read data. The master can notify the slave that communication is or is not interrupted at some midpoint, on the basis of the second bit of the preamble. The present technology can be applied to a bus IF that communicates pursuant to, for example, the specification of I3C.

First claim

The invention claimed is:

1. A communication device, comprising:
transmission and reception circuitry configured to communicate with an external communication device, including transmitting and receiving data via a data signal line and transmitting a clock via a clock signal line; and
control circuitry configured to
detect at least one of an acknowledgement signal or an absence of an acknowledgement signal transmitted from the external communication device in response to received data by the transmission and reception circuitry,
in a case where the control circuitry detects the absence of an acknowledgement signal, cause the transmission and reception circuitry to prevent a conflict for at least a first predetermined number of bits following the absence of an acknowledgement signal, and
detect an occurrence of an error in the received data by comparing a first bit sequence following a preamble of the received data to a second bit sequence corresponding to a data type designated by the preamble, and
in a case where the occurrence of the error is detected, cause the transmission and reception circuitry to transmit the clock for a first duration corresponding to at least a second predetermined number of bits following the preamble.

2. The communication device according to claim 1 , wherein when the preamble of the received data specifies transmission of a cyclic redundancy check (CRC) word, the CRC word including a token and a CRC-5, and the control circuitry detects an occurrence of at least one of a token error or a CRC error on the basis of the first bit sequence, the transmission and reception circuitry transmits a command signal after transmitting the clock for a second duration according to at least a number of bits in the CRC word and after transmitting an additional clock for the first duration, the second predetermined number of bits corresponding to a difference between the number of bits in the CRC word and a number of bits in the received data.

3. The communication device according to claim 2 , wherein the control circuitry ignores the received data for at least a period during transmission of the additional clock.

4. The communication device according to claim 3 , wherein the transmission and reception circuitry transmits the command signal at a timing of a second bit of a preamble of the data transmitted.

5. The communication device according to claim 2 , wherein the transmission and reception circuitry drives the data signal line from a bit immediately after receiving a cyclic redundancy check (CRC) word transmitted by the external communication device driving the data signal line.

6. The communication device according to claim 1 , wherein the control circuitry is further configured to detect the at least one of the acknowledgement signal or the absence of the acknowledgement signal on the preamble of the received data after a read command, and to detect the occurrence of an error in the received data on a cyclic redundancy check (CRC) word of the received data.

7. The communication device according to claim 1 , wherein the control circuitry is configured to detect that the error has occurred if a number of bits in the second bit sequence is smaller than a number of bits in the first bit sequence.

8. The communication device according to claim 1 , wherein
the control circuitry is configured to detect, by the comparing, that the error has occurred if a first one-bit error occurs in a first bit of the preamble, and
the detection of the absence of the acknowledgement signal by the control circuitry is a result of a second one-bit error in a second bit of the preamble transmitted from the external communication device.

9. The communication device according to claim 1 , wherein the transmission and reception circuitry drives a second bit of a preamble transmitted or received following a read data.

10. The communication device according to claim 1 , wherein the transmission and reception circuitry transmits a command instructing to either terminate or restart communication in a particular communication mode following a conflict prevention clock period, wherein the conflict prevention clock period has a duration corresponding to at least the first predetermined number of bits following the absence of an acknowledgement signal.

11. The communication device according to claim 1 , wherein the control circuitry includes a state machine configured to ignore a conflict prevention clock period having a duration corresponding to at least the first predetermined number of bits following the absence of an acknowledgement signal.

12. The communication device according to claim 1 , wherein the transmission and reception circuitry transmits a number of clock cycles when the absence of an acknowledgement signal is detected, the number of clock cycles being the same as the first predetermined number of bits following the absence of an acknowledgement signal.

13. The communication device according to claim 1 , wherein
the transmission and reception circuitry is able to transmit the data and receive the acknowledgement signal a standard data rate (SDR) mode in which data communication is conducted at a first transfer rate, and at least one high data rate (HDR) mode in which data communication is conducted at a second transfer rate, the second transfer rate being higher than the first transfer rate, and
the at least one HDR mode includes a plurality of additional modes in which the transmission and reception circuitry is capable of communicating, the plurality of additional modes including: a double data rate mode, a ternary symbol pure-bus mode, and a ternary symbol legacy-inclusive-bus mode.

14. The communication device according to claim 13 , wherein the communication device is further configured to switch a mode of the external communication device via a mode change signal.

15. The communication device according to claim 13 , wherein the transmission and reception circuitry transmits a command giving an instruction to restart communication in the at least one HDR mode after the first duration has elapsed.

16. The communication device according to claim 13 , wherein the transmission and reception circuitry transmits a command giving an instruction to exit the at least one HDR mode after the first duration has elapsed.

17. The communication device according to claim 13 , wherein the control circuitry is configured to detect an error in a preamble immediately after transmitting a read command in the at least one HDR mode and immediately before a read data.

18. The communication device according to claim 1 , wherein the control circuitry detects, by the comparing, the error by performing parity check on the data received by the transmission and reception circuitry wherein a first parity bit contained in the data is an even-numbered parity and a second bit contained in the data is an odd-numbered parity.

19. A communication system, comprising:
a first communication device, including:
first transmission and reception circuitry configured to communicate, including transmitting and receiving data via a data signal line and transmitting a clock via a clock signal line, and
control circuitry configured to
detect an occurrence of an error in received data by the transmission and reception circuitry by comparing a first bit sequence following a preamble of the received data to a second bit sequence corresponding to a data type designated by the preamble,
in a case where the occurrence of the error is detected, cause the first transmission and reception ci

Assignees

• Sony Corp

Inventors

• Takahashi Hiroo
• Yokokawa Takashi
• Lee Sonfun
• Koshisaka Naohiro

Classifications

• H04L7/041

  using special codes as synchronising signal · CPC title

• H04L2001/125

  Arrangements for preventing errors in the return channel · CPC title

• H04L1/0061 Primary

  Error detection codes · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F2213/0016

  Inter-integrated circuit (I2C) · CPC title