Analog-to-digital converter and sensor arrangement including the same

Patent metadata

Field	Value
Publication number	US-10892773-B2
Application number	US-202016811357-A
Country	US
Kind code	B2
Filing date	Mar 6, 2020
Priority date	Mar 7, 2019
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

A sigma-delta analog-to-digital converter including a gain element connected to an integrator. The gain element switches between different gain values during consecutive phases of a clock signal having a different number of clock cycles. A counter is configured to count with a different increment step size dependent on the first and second gain values. The converter may be part of a sensor arrangement with a temperature sensor.

First claim

What is claimed is:

1. An analog-to-digital converter, comprising:
an input terminal for an analog signal to be converted;
a first output terminal for a digital signal representing the analog signal to be converted;
a terminal for a reference signal;
a summing node connected to the input terminal for the analog signal to be converted, the summing node having a second output terminal;
an integrator connected downstream of the summing node;
a comparator connected downstream of the integrator and having a terminal for a clock signal and further having an output;
a feedback loop including a switch controlled by the output of the comparator, the switch connected between an input of the summing node and the terminal for the reference signal;
a gain element connected between the second output terminal of the summing node and the integrator, the gain element configured to switch between a first gain and a second gain, the first gain being different from the second gain, wherein the gain element is configured to operate with the first gain during a first number of cycles of the clock signal and to operate with the second gain during a consecutive second number of cycles of the clock signal; and
a counter connected downstream from the comparator, the counter configured to selectively count one of a first increment step size and a second increment step size in response to a signal from the comparator and dependent on one of the first gain or second gain, the counter connected to the first output terminal to provide the digital signal.

2. The analog-to-digital converter according to claim 1 , wherein the first number of cycles of the clock signal is larger than the second number of cycles of the clock signal, and wherein the first gain is larger than the second gain.

3. The analog-to-digital converter according to claim 2 , wherein the first increment step size is larger than the second increment step size, wherein the first increment step size is selected in response to the first gain, and wherein the second increment step size is selected in response to the second gain.

4. The analog-to-digital converter according claim 1 , wherein the integrator comprises an amplifier, a capacitor coupled between an input and an output of the amplifier, and a first resistor and a second resistor of different resistance selectively connected to the input of the amplifier and the capacitor in response to the selected one of the first gain and second gain.

5. The analog-to-digital converter according to claim 4 , further comprising a switch connected in parallel to the capacitor and configured to reset the integrator at the beginning of a conversion period.

6. The analog-to-digital converter according to claim 1 , wherein the first gain and second gain have a ratio, and wherein the first increment step size and the second increment step size of the counter have the same ratio.

7. The analog-to-digital converter according claim 1 , wherein the analog signal is a constant signal or a substantially constant signal during a conversion period comprising the first number of cycles of the clock signal and the second number of cycles of the clock signal.

8. The analog-to-digital converter according to claim 1 , further comprising a switch connected between a terminal for the clock signal and a clock input terminal of the counter, the switch comprising a control terminal connected downstream the comparator.

9. The analog-to-digital converter according to claim 1 , wherein the summing node comprises a summer comprising a first input terminal connected to the analog signal and a second input terminal, wherein the summer is configured that the signal at the second input terminal is subtracted from the analog signal.

10. The analog-to-digital converter according to claim 1 , comprising:
an operational amplifier having an inverting input and a non-inverting input;
an output of the operational amplifier connected through an integrating capacitor to the inverting input of the operational amplifier;
a first and a second resistor of different resistance connected to the inverting input of the operational amplifier through respective switches, wherein the first resistor has a resistance of R and the second resistor has a resistance of X*R, and wherein the counter is configured to count by an increment of X steps when the switch connected to the first resistor is conductive and the counter is configured to count by an increment of 1 step when the switch connected to the second resistor is conductive.

11. A sensor arrangement, comprising:
a sensor element configured to generate a variable output voltage;
a voltage generator configured to generate a constant voltage independent from temperature;
the analog-to-digital converter according to claim 1 , wherein the sensor element is connected to the input terminal for an analog signal of the analog-to-digital converter and the voltage generator is connected to the terminal for a reference signal of the analog-to-digital converter.

12. The sensor arrangement according to claim 11 , wherein the sensor element comprises at least one of:
a temperature sensor configured to generate an output voltage dependent from temperature; or
a pressure sensor configured to generate an output voltage dependent from a pressure exerted on the pressure sensor;
a hall sensor configured to generate an output voltage dependent from the hall effect.

13. The sensor arrangement according to claim 11 , wherein the sensor element is configured to generate a variable output voltage that is constant during a conversion cycle.

Assignees

• Tdk Electronics Ag

Inventors

• Petersen Henning
• Zou Lei

Classifications

• H03M3/43

  the quantiser being a single bit one · CPC title

• H03M3/484

  by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path · CPC title

• H03M3/458 Primary

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/482 Primary

  by adapting the quantisation step size · CPC title