Back-side illuminated image sensor

Patent metadata

Field	Value
Publication number	US-10892292-B2
Application number	US-201916386826-A
Country	US
Kind code	B2
Filing date	Apr 17, 2019
Priority date	Oct 7, 2016
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

First claim

The invention claimed is:

1. A back-side illuminated image sensor, comprising memory regions formed in a semiconductor wafer, each memory region being located between two opaque walls which extend into the semiconductor wafer from a rear surface of the semiconductor wafer and are in contact with an opaque screen arranged at the rear surface of the semiconductor wafer to cover the memory region, wherein each opaque wall is separated from the memory region by a polysilicon layer.

2. The sensor of claim 1 , wherein, for each memory region, the opaque walls and the opaque screen are conductive and are configured for connection to a node of application of a bias potential.

3. The sensor of claim 1 , wherein the opaque walls and the opaque screen are made of tungsten and the opaque walls have a thickness in the range from 50 to 200 nm.

4. The sensor of claim 1 , wherein the opaque walls are separated from the memory region by a layer of hafnium oxide.

5. The sensor of claim 1 , wherein the polysilicon layer is separated from the memory region by a silicon oxide layer.

6. The sensor of claim 5 , wherein the opaque walls are separated from the polysilicon layer by a layer of hafnium oxide.

7. A back-side illuminated image sensor, comprising:
a semiconductor wafer having a front surface and a rear surface;
a pair of trenches extending completely through the semiconductor wafer between the front and rear surfaces, said pair of trenches delimiting a memory region within the semiconductor wafer for a pixel that receives light through the rear surface;
a layer of polysilicon material on side walls of each trench and at a front of the trench adjacent the front surface;
an opaque wall in each trench, the opaque wall surrounded inside the trench by the layer of polysilicon material; and
an opaque screen arranged at the rear surface of the semiconductor wafer to cover the memory region and in contact with each opaque wall.

8. The sensor of claim 7 , wherein the opaque walls and the opaque screen are made of an electrically conductive material.

9. The sensor of claim 8 , wherein the electrically conductive material is tungsten.

10. The sensor of claim 7 , further comprising a layer of hafnium oxide positioned between the opaque wall and the memory region.

11. The sensor of claim 7 , further comprising layer of silicon oxide positioned between the layer of polysilicon material and the memory region.

12. The sensor of claim 11 , further comprising a layer of hafnium oxide positioned between the opaque wall and the layer of polysilicon.

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Benoit Daniel
• Hinsinger Olivier
• Gourvest Emmanuel

Classifications

• H10F39/8067

  Reflectors · CPC title

• H10F39/8057

  Optical shielding · CPC title

• H10F39/811

  Interconnections · CPC title

• H10F39/807

  Pixel isolation structures · CPC title

• H10F39/805

  Coatings · CPC title