Frame-level resynchronization between a display panel and a display source device for full and partial frame updates

Patent metadata

Field	Value
Publication number	US-10891887-B2
Application number	US-201816147383-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

Technology for a display source device is described. The display source device can receive a frame start indication from a display panel at a start of a frame. The display source device can align a timing of the display source device to a timing of the display panel based on the frame start indication received from the display panel to obtain frame-level synchronization between the display source device and the display panel. The display source device can send one or more frame update regions to the display panel in accordance with the timing of the display source device that is aligned to the timing of the display panel.

First claim

What is claimed is:

1. A display source device, comprising logic to:
receive a frame start indication from a display panel at a start of a frame;
align a timing of the display source device to a timing of the display panel based on the frame start indication received from the display panel to obtain frame-level synchronization between the display source device and the display panel;
send one or more frame update regions to the display panel in accordance with the timing of the display source device that is aligned to the timing of the display panel;
send a plurality of partial frame update regions to the display panel as a burst in accordance with the timing of the display source device that is aligned with the timing of the display panel; and
enter a low power mode at the display source device after the plurality of partial frame update regions are sent to the display panel.

2. The display source device of claim 1 , further including logic to:
send the plurality of partial frame update regions asynchronously after the start of the frame in raster order; and
enter the low power mode for a remaining duration of the frame.

3. The display source device of claim 1 , wherein each partial frame update region in the plurality of partial frame update regions is associated with a start of the partial frame update region and an end of the partial frame update region.

4. The display source device of claim 1 , wherein the plurality of partial frame update regions are sent prior to display of the partial frame update regions at the display panel.

5. The display source device of claim 1 , further including logic to:
receive a second frame start indication from the display panel when the display source device is in the low power mode;
transition from the low power mode to a normal power mode after the second frame start indication is received from the display panel;
realign the timing of the display source device to the timing of the display panel based on the second frame start indication received from the display panel; and
send new frame data to the display panel after entering the normal power mode when the display source device includes new frame data to send to the display panel.

6. The display source device of claim 1 , wherein the logic is configured to receive the frame start indication from the display panel when the display panel enters a Panel Self Refresh (PSR) mode.

7. The display source device of claim 1 , further including logic to send a full frame update region directly from the display source device to the display panel while avoiding a frame buffer, wherein the full frame update region is sent with an indication that instructs the display panel to bypass reading the full frame update region from the frame buffer.

8. The display source device of claim 1 , further including logic to send a full frame update region directly from the display source device to the display panel while avoiding a frame buffer, wherein the full frame update region is sent with an indication that the full frame update region is to be immediately followed by another full frame update region, and the indication instructs the display panel to bypass reading the full frame update region frame the frame buffer and writing the full frame update region to the frame buffer.

9. A display panel, comprising logic to:
send a frame start indication to a display source device for a start of a frame, wherein a timing of the display source device is aligned to a timing of the display panel based on the frame start indication to obtain frame-level synchronization between the display source device and the display panel;
receive one or more frame update regions from the display source device in accordance with the timing of the display source device that is aligned to the timing of the display panel; and
receive a plurality of partial frame update regions from the display source device as a burst in accordance with the timing of the display source device that is aligned with the timing of the display panel, wherein the plurality of partial frame update regions are received prior to display of the partial frame update regions at the display panel.

10. The display panel of claim 9 , further including logic to receive, from the display source device, the plurality of partial frame update regions asynchronously after the start of the frame in raster order.

11. The display panel of claim 9 , wherein each partial frame update region in the plurality of partial frame update regions is associated with a start of the partial frame update region, an end of the partial frame update region and a cyclic redundancy check for the partial frame update region.

12. The display panel of claim 9 , further including logic to:
send a second frame start indication to the display source device when the display source device is in a low power mode, wherein the second frame start indication causes the display source device to transition from the low power mode to a normal power mode and realign the timing of the display source device to the timing of the display panel; and
receive new frame data from the display source device after the display source device has transitioned to the normal power mode and includes new frame data to send to the display panel.

13. The display panel of claim 9 , wherein the logic is configured to send the frame start indication to the display source device when the display panel enters a Panel Self Refresh (PSR) mode.

14. The display panel of claim 9 , further including logic to:
receive a full frame update region directly from the display source device that avoids a frame buffer, wherein the full frame update region is received with an indication that instructs the display panel to bypass reading the full frame update region from the frame buffer;
write the full frame update region to the frame buffer; and
display the full frame update region as received from the display source device.

15. The display panel of claim 9 , further including logic to:
receive a full frame update region directly from the display source device that avoids a frame buffer, wherein the full frame update region is received with an indication that the full frame update region is to be immediately followed by another full frame update region;
avoid writing the full frame update region to the frame buffer based on the indication received from the display source device;
avoid reading the full frame update region from the frame buffer based on the indication received from the display source device; and
display the full frame update region as received from the display source device.

16. A content display system, comprising:
a display panel;
a display source device; and
a frame buffer,
wherein the display panel comprises logic to:
send a frame start indication to the display source device,

wherein the display source device comprises logic to:
align a timing of the display source device to a timing of the display panel based on the frame start indication received from the display panel to obtain frame-level synchronization between the display source device and the display panel; and
send, via the frame buffer or by avoiding the frame buffer, one or more frame update regions to the display panel in accordance with the timing of the display source device that is aligned to the timing of the display panel.

17. The content display system of claim 16 , wherein the display source device further includes logic to:
send a plurality of partial frame update regions to the display panel as a burst in accordance with t

Assignees

• Intel Corp

Inventors

• Ansari Nausheen
• Kwa Seh
• Diefenbaugh Paul S
• Johnston Robert

Classifications

• G09G2310/04

  Partial updating of the display screen · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2320/0261

  in the context of movement of objects on the screen or movement of the observer relative to the screen · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title