Pre-pass surface analysis to achieve adaptive anti-aliasing modes

Patent metadata

Field	Value
Publication number	US-10891705-B2
Application number	US-201916269232-A
Country	US
Kind code	B2
Filing date	Feb 6, 2019
Priority date	Apr 10, 2017
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.

First claim

What is claimed is:

1. A system comprising:
a display to output visual content; and
a semiconductor package apparatus coupled to the display, the semiconductor package apparatus including:
a substrate; and
logic coupled to the substrate, the logic to:
determine a position associated with one or more polygons in unresolved surface data corresponding to the visual content,
select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position, and
uniformly resolve the unresolved surface data at the position in accordance with the selected anti-aliasing sample rate.

2. The system of claim 1 , wherein the position is to be a bounding box.

3. The system of claim 2 , wherein the semiconductor package apparatus further includes a graphics pipeline including a render pre-pass stage and a render pass stage, wherein the bounding box is to be determined and the anti-aliasing sample rate is to be selected at the render pre-pass stage, and wherein the unresolved surface data is to be resolved at the render pass stage of the graphics pipeline.

4. The system of claim 1 , wherein the position is a display screen coordinate.

5. The system of claim 4 , wherein the semiconductor package apparatus further includes a graphics pipeline including a post-processor pre-pass stage and an image post-processor stage, wherein the display screen coordinate is to be determined and the anti-aliasing sample rate is to be selected at the post-processor pre-pass stage, and wherein the unresolved surface data is to be resolved at the image post-processor stage.

6. The system of claim 1 , wherein the selected anti-aliasing sample rate is to vary across a plurality of pixels, and
wherein the logic is to:
select a first anti-aliasing mode having a first sample rate if the one or more polygons are in one or more of an intersection state or a motion state at the position;
select a second anti-aliasing mode having a second sample rate if the one or more polygons are in an edge state at the position; and
select a third anti-aliasing mode having a third sample rate if the one or more polygons are in not in the intersection state, the motion state or the edge state at the position, wherein the second sample rate is to be greater than the first sample rate, and wherein the third sample rate is to be greater than the second sample rate.

7. An apparatus comprising:
a substrate; and
logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic to:
determine a position associated with one or more polygons in unresolved surface data,
select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position, and
uniformly resolve the unresolved surface data at the position in accordance with the selected anti-aliasing sample rate.

8. The apparatus of claim 7 , wherein the position is to be a bounding box.

9. The apparatus of claim 8 , further including a graphics pipeline including a render pre-pass stage and a render pass stage, wherein the bounding box is to be determined and the anti-aliasing sample rate is to be selected at the render pre-pass stage, and wherein the unresolved surface data is to be resolved at the render pass stage of the graphics pipeline.

10. The apparatus of claim 7 , wherein the position is a display screen coordinate.

11. The apparatus of claim 10 , further including a graphics pipeline including a post-processor pre-pass stage and an image post-processor stage, wherein the display screen coordinate is to be determined and the anti-aliasing sample rate is to be selected at the post-processor pre-pass stage, and wherein the unresolved surface data is to be resolved at the image post-processor stage.

12. The apparatus of claim 7 , wherein the selected anti-aliasing sample rate is to vary across a plurality of pixels, and
wherein the logic is to:
select a first anti-aliasing mode having a first sample rate if the one or more polygons are in one or more of an intersection state or a motion state at the position;
select a second anti-aliasing mode having a second sample rate if the one or more polygons are in an edge state at the position; and
select a third anti-aliasing mode having a third sample rate if the one or more polygons are in not in the intersection state, the motion state or the edge state at the position, wherein the second sample rate is to be greater than the first sample rate, and wherein the third sample rate is to be greater than the second sample rate.

13. A method comprising:
determining, via logic implemented in one or more of configurable logic or fixed-functionality hardware logic, a position associated with one or more polygons in unresolved surface data, wherein the unresolved surface data corresponds to visual content to be output to a display;
selecting, via the logic, an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position; and
uniformly resolving, via the logic, the unresolved surface data at the position in accordance with the selected anti-aliasing sample rate.

14. The method of claim 13 , wherein the position is a bounding box.

15. The method of claim 14 , wherein the bounding box is determined and the anti-aliasing sample rate is selected at a render pre-pass stage of a graphics pipeline, and wherein the unresolved surface data is resolved at a render pass stage of the graphics pipeline.

16. The method of claim 13 , wherein the position is a display screen coordinate.

17. The method of claim 16 , wherein the display screen coordinate is determined and the anti-aliasing sample rate is selected at a post-processor pre-pass stage of a graphics pipeline, and wherein the unresolved surface data is resolved at an image post-processor stage of the graphics pipeline.

18. The method of claim 13 , wherein the selected anti-aliasing sample rate is to vary across a plurality of pixels, and wherein selecting the anti-aliasing sample rate is to include:
selecting a first anti-aliasing mode having a first sample rate if the one or more polygons are in one or more of an intersection state or a motion state at the position;
selecting a second anti-aliasing mode having a second sample rate if the one or more polygons are in an edge stage at the position; and
selecting a third anti-aliasing mode having a third sample rate if the one or more polygons are in not in the intersection state, the motion state or the edge state at the position, wherein the second sample rate is to be greater than the second sample rate, and wherein the third sample rate is to be greater than the second sample rate.

19. At least one computer readable storage medium comprising a set of instructions, which when executed, cause a computing system to:
determine a position associated with one or more polygons in unresolved surface data, wherein the unresolved surface data corresponds to visual content to be output to a display;
select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position; and
uniformly resolve the unresolved surface data at the position in accordance with the selected anti-aliasing sample rate.

20. The at least one computer readable storage medium of claim 19 , wherein the position is to be a bounding box.

21. The at least one computer readable storage medium of claim 20 , wherein the bounding box is to be determined and the anti

Assignees

• Intel Corp

Inventors

• Appu Abhishek R
• Ray Joydeep
• Doyle Peter L
• Maiyuran Subramaniam
• Burke Devan
• Laws Philip R
• Ould-Ahmed-Vall Elmoustapha
• Koker Altug

Classifications

• G06T1/60

  Memory management · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title