Low-power type-C receiver with high idle noise and DC-level rejection

Patent metadata

Field	Value
Publication number	US-10890957-B2
Application number	US-201816181657-A
Country	US
Kind code	B2
Filing date	Nov 6, 2018
Priority date	Jun 19, 2015
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

Techniques for low-power USB Type-C receivers with high noise rejection are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to reject the incoming signal even when the incoming signal includes noise with a magnitude of more than 300 mVpp, and to operate in the presence of a VBUS charging current that is compliant with a USB-PD specification.

First claim

What is claimed is:

1. A device comprising:
a receiver circuit coupled to a Configuration Channel (CC) line of a Universal Serial Bus (USB) Type-C subsystem, wherein the receiver circuit is configured to:
reject an incoming signal on the CC line when the incoming signal comprises noise with a magnitude of more than 300 mVpp; and
operate in the presence of a VBUS charging current that is compliant with a USB-PD specification.

2. The device of claim 1 , wherein the incoming signal comprises the noise during idle condition.

3. The device of claim 1 , wherein the receiver circuit is configured to forgo generation of a wake-up signal based on the incoming signal when the incoming signal comprises the noise with the magnitude of more than 300 mVpp.

4. The device of claim 1 , wherein the receiver circuit comprises:
a capacitor coupled in series from the CC line to a restore node, the capacitor configured to block a DC component of the incoming signal on the CC line;
a restoration circuit coupled to the restore node and configured to generate a shifted voltage of the incoming signal that is shifted to a first reference voltage; and
a slicer circuit coupled to the restore node and configured to compare the shifted voltage to a second reference voltage.

5. The device of claim 4 , wherein the first reference voltage and the second reference voltage are configured to define a voltage threshold at which an output of the slicer circuit is toggled to indicate that the incoming signal is not noise.

6. The device of claim 5 , wherein the voltage threshold is up to 500 mVpp.

7. The device of claim 6 , wherein the device is configured to remain in a sleep state when the shifted voltage is at or below the voltage threshold.

8. The device of claim 1 , wherein the magnitude of the noise is in a first range from 300 mVpp to 350 mVpp, a second range from 350 mVpp to 400 mVpp, a third range from 400 mVpp to 450 mVpp, or a fourth range from 450 mVpp to 500 Vpp.

9. An integrated circuit (IC) controller comprising:
a Universal Serial Bus (USB) Type-C subsystem; and
a receiver circuit coupled to a Configuration Channel (CC) line of the USB Type-C subsystem, wherein the receiver circuit is configured to:
reject an incoming signal on the CC line when the incoming signal comprises noise with a magnitude of more than 300 mVpp; and
operate in the presence of a VBUS charging current that is compliant with a USB-PD specification.

10. The IC controller of claim 9 , wherein the incoming signal comprises the noise during idle condition.

11. The IC controller of claim 9 , wherein the receiver circuit is configured to forgo generation of a wake-up signal based on the incoming signal when the incoming signal comprises the noise with the magnitude of more than 300 mVpp.

12. The IC controller of claim 9 , wherein the IC controller is disposed on an IC chip that includes the USB Type-C subsystem, and wherein the USB Type-C subsystem includes the receiver circuit.

13. A Universal Serial Bus (USB) Type-C cable, comprising:
a first Type-C connector disposed at a first end of the Type-C cable; and
a first integrated circuit (IC) chip disposed within the Type-C cable and coupled to a Configuration Channel (CC) line of the first Type-C connector, wherein the first IC chip includes a first receiver circuit configured at least to:
reject an incoming signal on the CC line when the incoming signal comprises noise with a magnitude of more than 300 mVpp; and
operate in the presence of a VBUS charging current on a VBUS line of the first Type-C connector, wherein the VBUS charging current is compliant with a USB-PD specification.

14. The USB Type-C cable of claim 13 , wherein the first receiver circuit comprises:
a capacitor coupled in series from the CC line to a restore node, the capacitor configured to block a DC component of the incoming signal on the CC line;
a restoration circuit coupled to the restore node and configured to generate a shifted voltage of the incoming signal that is shifted to a first reference voltage; and
a slicer circuit coupled to the restore node and configured to compare the shifted voltage to a second reference voltage.

15. The USB Type-C cable of claim 14 , wherein the first reference voltage and the second reference voltage are configured to define a voltage threshold at which an output of the slicer circuit is toggled to indicate that the incoming signal is not noise.

16. The USB Type-C cable of claim 15 , wherein the voltage threshold is up to 500 mVpp.

17. The USB Type-C cable of claim 13 , wherein the incoming signal comprises the noise during idle condition.

18. The USB Type-C cable of claim 13 , wherein the USB Type-C cable further comprises a second Type-C connector disposed at a second end of the Type-C cable, wherein the second Type-C connector comprises a second IC chip that includes a second receiver circuit.

19. The USB Type-C cable of claim 13 , wherein the first Type-C connector is a Type-C receptacle.

20. The USB Type-C cable of claim 13 , further comprising a second USB 2.0 connector disposed at a second end of the Type-C cable.

Assignees

• Cypress Semiconductor Corp

Inventors

• Agarwal Rishi
• Bodnaruk Nicholas Alexander

Classifications

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title

• G06F1/22 Primary

  Means for limiting or controlling the pin/gate ratio · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/38

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title