Detection circuit for an active discharge circuit of an X-capacitor, related active discharge circuit, integrated circuit and method

Patent metadata

Field	Value
Publication number	US-10890606-B2
Application number	US-201916443439-A
Country	US
Kind code	B2
Filing date	Jun 17, 2019
Priority date	Nov 4, 2014
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

An active discharge circuit discharges an X capacitor and includes a sensor circuit that generates a sensor signal indicative of an AC voltage at the X capacitor. A processing unit generates a reset signal as a function of a comparison signal. A comparator circuit generates the comparison signal by comparing the sensor signal with a threshold. A timer circuit sets a discharge enable signal to a first logic level when the timer circuit is reset via a reset signal. The timer circuit determines the time elapsed since the last reset and tests whether the time elapsed exceeds a given timeout value. If the time elapsed exceeds the given timeout value, the timer circuit sets the discharge enable signal to a second logic level. A dynamic threshold generator circuit varies the threshold of the comparator circuit as a function of the sensor signal.

First claim

The invention claimed is:

1. A detection circuit, comprising:
a sensor circuit configured to be coupled to an X capacitor, said sensor circuit configured to generate a sensor signal indicative of a voltage at said X capacitor;
a window comparator configured to compare the sensor signal with a lower threshold value and an upper threshold value and generate a comparison signal indicating whether said sensor signal is between the lower threshold value and the upper threshold value;
a timer circuit configured to:
set a discharge enable signal to a first logic level in response to said timer circuit being reset via a reset signal;
determine a time elapsed since said timer circuit has been reset via the reset signal;
determine whether said time elapsed exceeds a given timeout value; and; the prior art fails to disclose the further inclusion of the combination of
if said time elapsed exceeds said given timeout value, set said discharge enable signal to a second logic level to cause an active discharge circuit to discharge the X capacitor;

an elaboration circuit configured to generate said reset signal for said timer circuit as a function of said comparison signal, the elaboration circuit configured to generate, based on said comparison signal, a first control signal indicating whether the sensor signal is increasing and a second control signal indicating whether the sensor signal is decreasing; and
a dynamic threshold generator circuit configured to generate said lower threshold value and said upper threshold value of said window comparator based on the sensor signal, and said dynamic threshold generator circuit further configured to:
vary said lower threshold value and said upper threshold value of said window comparator as a first function of said first control signal from said elaboration circuit to increase a first value of a smaller one of the lower threshold value and the upper value to a first new value that is greater than a larger one of the lower threshold value and upper threshold value in response to the first control signal indicating the sensor signal is greater than the upper threshold value and the lower threshold value; and
vary said lower threshold value and said upper threshold value of said window comparator as a second function of said second control signal from said elaboration circuit to decrease a second value of the larger one of the lower threshold value and the upper threshold value to a second new value that is less than the value of the smaller one of the lower threshold value and the upper threshold value in response to the second control signal indicating the sensor signal is less than the upper threshold value and the lower threshold value.

2. The detection circuit of claim 1 , wherein the elaboration circuit is further configured to:
detect whether said comparison signal includes both a leading edge and a falling edge;
in the case where said comparison signal includes both said leading edge and said falling edge, determine a time elapsed between said leading edge and said falling edge;
detect whether said time elapsed between said leading edge and said falling edge is smaller than a given time threshold value; and
reset said timer circuit via said reset signal in response to detecting that said time elapsed between said leading and said falling edge is smaller than said given time threshold value.

3. The detection circuit of claim 1 , wherein said elaboration circuit is configured to:
detect an edge of said comparison signal; and
reset said timer circuit via said reset signal in response to detecting the edge of said comparison signal.

4. The detection circuit of claim 1 , wherein said window comparator comprises:
a first comparator configured to generate a first comparison signal indicating whether said sensor signal is greater than the lower threshold value; and
a second comparator configured to generate a second comparison signal indicating whether said sensor signal is greater than the upper threshold value.

5. The detection circuit of claim 4 , wherein said elaboration circuit is further configured to:
generate, based on said first comparison signal and said second comparison signal from the window comparator, the first control signal indicating whether said sensor signal is greater than both of said upper threshold value and lower threshold value;
generate, based on said first comparison signal and said second comparison signal from the window comparator, the second control signal indicating whether said sensor signal is smaller than both of said upper threshold value and said lower threshold value; and
reset said timer circuit via said reset signal in response to said first comparison signal and said second comparison signal indicating that said sensor signal is greater than both of said upper threshold value and lower threshold value.

6. The detection circuit of claim 5 , wherein said dynamic threshold generator circuit is further configured:
to determine, based on the first control signal and the second control signal, whether said first comparison signal and said second comparison signal indicate that said sensor signal is greater than both of said upper threshold value and lower threshold value, smaller than both of said upper threshold value and lower threshold value, or between said upper threshold value and lower threshold value;
in response to said first control and second control signal indicating that said sensor signal is greater than both of said upper threshold value and lower threshold value, to increase the lower threshold value to a new value that is greater than a current value of the upper threshold value; and
in response to said first control signal and second control signal indicating that said sensor signal is smaller than both of said upper threshold value and lower threshold value, to decrease the upper threshold value to a value that is smaller than a current value of the lower threshold value.

7. A device, comprising:
a discharge circuit configured to discharge an X capacitor; and
a detection circuit coupled to the discharge circuit and including:
a sensor circuit configured to be coupled to the X capacitor, said sensor circuit configured to generate a sensor signal indicative of a voltage at said X capacitor;
a window comparator configured to compare the sensor signal with a lower threshold value and an upper threshold value and generate a comparison signal indicating whether said sensor signal is between the lower threshold value and the upper threshold value;
a timer circuit configured to:
set a discharge enable signal to a first logic level in response to said timer circuit being reset via a reset signal;
determine a time elapsed since said timer circuit has been reset via the reset signal;
determine whether said time elapsed exceeds a given timeout value; and if said time elapsed exceeds said given timeout value, set said discharge enable signal to a second logic level to cause an active discharge circuit to discharge the X capacitor;

an elaboration circuit configured to generate said reset signal for said timer circuit as a function of said comparison signal, the elaboration circuit configured to generate, based on said comparison signal, a first control signal indicating whether the sensor signal is increasing and a second control signal indicating whether the sensor signal is decreasing; and
a dynamic threshold generator circuit configured to generate said lower threshold value and upper threshold value of said window comparator based on the sensor signal, and said dynamic threshold generator circuit further configured to:
vary said lower threshold value and upper threshold value of said window comparator as a first function of said first control signal from said elabora

Assignees

• St Microelectronics Srl

Inventors

• Gobbi Massimiliano
• Bellomo Ignazio Salvatore
• Tripodi Domenico
• Borrello Antonio
• Bianco Alberto

Classifications

• H02J7/92 Primary

  with prioritisation of loads or sources · CPC title

• G01R19/16557 Primary

  Logic probes, i.e. circuits indicating logic state (high, low, O); (modifications of electronic switches or gates for indicating state of switch H03K17/18) · CPC title

• H02M1/322

  Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock · CPC title

• H02J7/345

  using capacitors as storage or buffering devices · CPC title

• G01R19/04

  Measuring peak values {or amplitude or envelope} of AC or of pulses · CPC title