Shift register and method for driving the same, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-10885853-B2
Application number	US-201816205305-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Jan 31, 2018
Publication date	Jan 5, 2021
Grant date	Jan 5, 2021

Abstract

A shift register and a method for driving the same, a gate driving circuit and a display device. The shift register includes: an input sub-circuit configured to provide a signal at the signal input terminal to the pull-up node under control of the first clock signal terminal; an output sub-circuit configured to provide a clock signal at the second clock signal terminal to the signal output terminal under control of the pull-up node; and a pull-down sub-circuit configured to provide a signal at the power supply terminal to the signal output terminal under control of the third clock signal terminal.

First claim

What is claimed is:

1. A shift register, comprising:
an input sub-circuit connected to a signal input terminal, a first clock signal terminal and a pull-up node, and configured to provide a signal at the signal input terminal to the pull-up node under control of the first clock signal terminal;
an output sub-circuit connected to the pull-up node, a second clock signal terminal and a signal output terminal, and configured to provide a clock signal at the second clock signal terminal to the signal output terminal under control of the pull-up node to pull down a potential of a signal output by the signal output terminal by a low level of the lock signal at the second clock signal terminal; and
a pull-down sub-circuit connected to the signal output terminal, a third clock signal terminal and a power supply terminal, and configured to provide a signal at the power supply terminal to the signal output terminal under control of the third clock signal terminal to pull down the potential of the signal output by the signal output terminal by a low level of the power signal at the power supply terminal.

2. The shift register according to claim 1 , wherein the input sub-circuit comprises a first transistor;
wherein a control electrode of the first transistor is connected to the first clock signal terminal, a first electrode of the first transistor is connected to the signal input terminal, and a second electrode of the first transistor is connected to the pull-up node.

3. The shift register according to claim 1 , wherein the output sub-circuit comprises a second transistor and a capacitor;
wherein:
a control electrode of the second transistor is connected to the pull-up node, a first electrode of the second transistor is connected to the second clock signal terminal, and a second electrode of the second transistor is connected to the signal output terminal; and
a first terminal of the capacitor is connected to the pull-up node, and a second terminal of the capacitor is connected to the signal output terminal.

4. The shift register according to claim 1 , wherein the pull-down sub-circuit comprises a third transistor;
wherein a control electrode of the third transistor is connected to the third clock signal terminal, a first electrode of the third transistor is connected to the signal output terminal, and a second electrode of the third transistor is connected to the power supply terminal.

5. The shift register according to claim 1 , wherein the input sub-circuit comprise a first transistor, the output sub-circuit comprises a second transistor and a capacitor, and the pull-down sub-circuit comprises a third transistor;
wherein:
a control electrode of the first transistor is connected to the first clock signal terminal, a first electrode of the first transistor is connected to the signal input terminal, and a second electrode of the first transistor is connected to a first terminal of the capacitor;
a control electrode of the second transistor is connected to the first terminal of the capacitor, a first electrode of the second transistor is connected to the second clock signal terminal, and a second electrode of the second transistor is connected to the signal output terminal;
a second terminal of the capacitor is connected to the signal output terminal; and
a control electrode of the third transistor is connected to the third clock signal terminal, a first electrode of the third transistor is connected to the signal output terminal, and a second electrode of the third transistor is connected to the power supply terminal.

6. The shift register according to claim 5 , wherein the first transistor, the second transistor, and the third transistor are N-type thin film transistors or P-type thin film transistors.

7. A gate driving circuit, comprising a plurality of cascaded shift registers;
wherein each of the shift registers comprises an input sub-circuit connected to a signal input terminal, a first clock signal terminal and a pull-up node, and configured to provide a signal at the signal input terminal to the pull-up node under control of the first clock signal terminal;
an output sub-circuit connected to the pull-up node, a second clock signal terminal and a signal output terminal, and configured to provide a clock signal at the second clock signal terminal to the signal output terminal under control of the pull-up node; and
a pull-down sub-circuit connected to the signal output terminal, a third clock signal terminal and a power supply terminal, and configured to provide a signal at the power supply terminal to the signal output terminal under control of the third clock signal terminal;
wherein the gate driving circuit further comprises a first clock signal source, a second clock signal source, a third clock signal source, a fourth clock signal source, a fifth clock signal source, and a sixth clock signal source;
wherein:
a signal input terminal of an N-th stage shift register is connected to a signal output terminal of an (N−1)-th stage shift register;
a first clock signal terminal of the (N−1)-th stage shift register is connected to the first clock signal source, a second clock signal terminal of the (N−1)-th stage shift register is connected to the second clock signal source, and a third clock signal terminal of the (N−1)-th stage shift register is connected to the fourth clock signal source;
a first clock signal terminal of the N-th stage shift register is connected to the second clock signal source, a second clock signal terminal of the N-th stage shift register is connected to the third clock signal source, and a third clock signal terminal of the N-th stage shift register is connected to the fifth clock signal source; and
a first clock signal terminal of an (N+1)-th stage shift register is connected to the third clock signal source, a second clock signal terminal of the (N+1)-th stage shift register is connected to the first clock signal source, and a third clock signal terminal of the (N+1)-th stage shift register is connected to the sixth clock signal source.

8. The gate driving circuit according to claim 7 , wherein:
periods and duty ratios of signals of the first clock signal source, the second clock signal source, and the third clock signal source are equal, and periods and duty ratios of signals of the fourth clock signal source, the fifth clock signal source, and the sixth clock signal source are equal; and
a period of the signal of the first clock signal source is equal to a period of the fourth clock signal source, and a duty ratio of the signal of the first clock signal source is greater than the duty ratio of the signal of the fourth clock signal source.

9. The gate driving circuit according to claim 7 , wherein the input sub-circuit comprises a first transistor;
wherein a control electrode of the first transistor is connected to the first clock signal terminal, a first electrode of the first transistor is connected to the signal input terminal, and a second electrode of the first transistor is connected to the pull-up node.

10. The gate driving circuit according to claim 7 , wherein the output sub-circuit comprises a second transistor and a capacitor;
wherein:
a control electrode of the second transistor is connected to the pull-up node, a first electrode of the second transistor is connected to the second clock signal terminal, and a second electrode of the second transistor is connected to the signal output terminal; and
a first terminal of the capacitor is connected to the pull-up node, and a second terminal of the capacitor is connected to the signal output terminal.

11. The gate driving circuit according to claim 7 , wherein the pull-down sub-circuit compris

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech
• Hefie Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Ying
• Li Meng
• Li Hongmin
• Wang Dong
• Tang Fengjing

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title