Wideband LO signal generation

Patent metadata

Field	Value
Publication number	US-10884449-B2
Application number	US-201916404032-A
Country	US
Kind code	B2
Filing date	May 6, 2019
Priority date	May 6, 2019
Publication date	Jan 5, 2021
Grant date	Jan 5, 2021

Abstract

An LO clock signal generator includes a fundamental mixer for mixing a source clock signal with a divided version of the source clock signal. The LO clock signal generator also includes a harmonic mixer for mixing the source clock signal with a third harmonic of a divided version of the source clock signal.

First claim

We claim:

1. A local oscillator (LO) clock signal generator, comprising:
a clock source for sourcing a source clock signal;
a first divider configured to divide the source clock signal in frequency into a divided source clock signal;
a first mixer configured to mix the source clock signal with the divided source clock signal to form a first up-converted clock signal;
a second mixer configured to mix the source clock signal with a third harmonic of the divided source clock signal to form a second up-converted clock signal;
a second divider configured to divide the second up-converted clock signal in frequency to form a third up-converted clock signal; and
an LO distribution network configured to divide the first up-converted clock signal in frequency to form a first LO output clock signal and to divide the third up-converted clock signal in frequency to form a second LO output clock signal.

2. The LO clock signal generator of claim 1 , wherein the first divider is an in-phase/quadrature-phase (I/Q) divider configured to divide the source clock signal by two to form an in-phase divided clock signal and a quadrature-phase divided clock signal, and wherein first mixer is further configured to mix the source clock signal with the in-phase divided clock signal to form the first up-converted clock signal, and wherein the second mixer is further configured to mix the source clock signal with the quadrature-phase divided clock signal to form the second up-converted clock signal.

3. The LO clock signal generator of claim 1 , wherein the clock source is a voltage-controlled oscillator.

4. The LO clock signal generator of claim 1 , wherein the first divider is a divide-by-two divider.

5. The LO clock signal generator of claim 4 , wherein the clock source is a differential clock source.

6. The LO clock signal generator of claim 5 , wherein the first mixer includes a pair of first load inductors coupled between a pair of output nodes for the first mixer and a power supply node, and wherein the second mixer includes a pair of second load inductors coupled between a pair of output nodes for the second mixer and the power supply node.

7. The LO clock signal generator of claim 6 , wherein the first pair of load inductors comprises a first loop in a first metal layer and a second loop in the first metal layer, wherein the second loop includes a first portion outside of the first loop and includes a second portion inside the first loop, and wherein the first portion of the second loop connects to the second portion of the second loop through a connecting lead in an adjacent metal layer to the first metal layer.

8. The LO clock signal generator of claim 7 , wherein the pair of second load inductors comprises a third loop in the first metal layer and a fourth loop in the first metal layer, and wherein the third loop and the fourth loop are both concentric with the first loop and the second loop.

9. The LO clock signal generator of claim 8 , wherein the third loop and the fourth loop are both within the first loop and the second loop.

10. The LO clock signal generator of claim 1 , wherein the second divider is a divide-by-two clock divider.

11. The LO clock signal generator of claim 10 , wherein the LO distribution network is configured divide the first up-converted clock signal by two to form the first LO output clock signal and to divide the third up-converted clock signal by two to form the second LO output clock signal.

12. The LO clock signal generator of claim 1 , further comprising:
a first amplifier for amplifying the first up-converted clock signal, and
a second amplifier for amplifying the second up-converted clock signal.

13. The LO clock signal generator of claim 12 , wherein the first amplifier is a first transconductance amplifier including a first pair of load inductors, and wherein the second amplifier is a second transconductance amplifier including a second pair of load inductors.

14. An LO clock signal generation method, comprising:
during a first mode of operation:
dividing a source clock signal in frequency to form a divided source clock signal;
mixing the source clock signal with the divided source clock signal to form a first up-converted clock signal; and
dividing the first up-converted clock signal in frequency to form a first local oscillator output clock signal;

during a second mode of operation:
mixing the source clock signal with a third harmonic of the divided source clock signal to form a second up-converted clock signal;
dividing the second up-converted clock signal in frequency to form a third up-converted clock signal; and
dividing the third up-converted clock signal in frequency to form a second local oscillator output clock signal.

15. The method of claim 14 , wherein dividing the source clock signal to form the divided source clock signal comprises dividing the source clock signal in frequency by two.

16. The method of claim 15 , wherein dividing the first up-converted clock signal in frequency to form the first local oscillator output clock signal comprises dividing the first up-converted clock signal in frequency by two.

17. The method of claim 15 , wherein dividing the second up-converted clock signal in frequency to form a third up-converted clock signal comprises dividing the second-up converted clock signal in frequency by two.

18. The method of claim 17 , wherein dividing the third up-converted clock signal in frequency to form the second local oscillator output clock signal comprising dividing the third up-converted clock signal in frequency by two.

19. The method of claim 14 , further comprising:
amplifying the first up-converted clock signal prior to the dividing of the first up-converted clock signal in frequency to form the first local oscillator output clock signal; and
amplifying the second up-converted clock signal prior to the dividing of the second up-converted clock signal in frequency to form the third up-converted clock signal.

20. An LO clock signal generator, comprising:
first means for frequency shifting a source clock signal into a first up-converted clock signal having a frequency that is one and one-half times larger than a source frequency for the source clock signal;
second means for frequency shifting the source clock signal into a second up-converted clock signal having a frequency that is two and one-half times larger than the source frequency;
a divide-by-two divider configured to divide the second up-converted clock signal into a third up-converted clock signal having a frequency that is one and one-fourth times larger than the source frequency; and
an LO distribution network configured to divide the first up-converted clock signal into a first LO output clock signal having a frequency that is three-fourths of the source frequency, the LO distribution network being further configured to divide the third up-converted clock signal into a second LO output clock signal having a frequency that is five-eighths the source frequency.

21. The LO clock signal generator of claim 20 , further comprising a clock source configured to source the source clock signal.

22. The LO clock signal generator of claim 21 , wherein the clock source comprises a voltage-controlled oscillator.

Assignees

• Qualcomm Inc

Inventors

• Khalili Alireza
• Emadi Mohammad
• Abdollahi-Alibeik Shahram
• Mostajeran Ali

Classifications

• G06K1/04

  controlled by sensing markings on the record carrier being punched · CPC title

• H03K5/01 Primary

  Shaping pulses (discrimination against noise or interference H03K5/125) · CPC title

• H03K21/026

  comprising logic circuits · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• H03D2200/0084

  Lowering the supply voltage and saving power · CPC title