Voltage-mode transmitter driver

Patent metadata

Field	Value
Publication number	US-10880133-B2
Application number	US-201815976545-A
Country	US
Kind code	B2
Filing date	May 10, 2018
Priority date	May 10, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

Devices and methods for finite impulse response (FIR) feed forward equalization (FFE) at a transmitter are provided. A voltage-mode driver circuit has a main driver and an equalization driver. The main driver drives the digital output signal based on a received digital input signal. The equalization function of the equalization driver is enabled or disabled for a short duration of time to provide at least one of FIR equalization and pre-emphasis to the digital output signal. Pre-emphasis is effected by enabling a low-resistance path of the equalization driver based on the digital input signal such that, when the low-resistance path is enabled, it reduces the transmission resistance for a short period of time.

First claim

The invention claimed is:

1. A transmitter driver circuit for transmitting a digital output signal, comprising:
a main driver for driving transmission of the digital output signal across a communication channel based on a received digital input signal;
an equalization driver arranged in parallel with the main driver, comprising a variable-resistance path for:
receiving the digital input signal; and
providing pre-emphasis to the digital output signal to increase the peak-to-peak amplitude of the digital output signal by, in response to changes in the amplitude of the digital input signal, reducing the resistance of the variable-resistance path for a predetermined period of time.

2. The transmitter driver circuit of claim 1 wherein the main driver operates in voltage mode and the digital output signal is a voltage-mode digital signal.

3. The transmitter driver circuit of claim 1 wherein the main driver operates in current mode and the digital output signal is a current-mode digital signal.

4. The transmitter driver circuit of claim 1 , wherein the equalization driver further comprises a finite impulse response (FIR) equalization circuit for providing FIR equalization to the digital output signal based on the data input signal.

5. The transmitter driver circuit of claim 4 , wherein the FIR equalization circuit further comprises one or more tap delays for generating one or more delayed input signals.

6. The transmitter driver circuit of claim 5 , wherein the one or more tap delays comprise a plurality of tap delays and the one or more delayed input signals comprise a plurality of delayed input signals.

7. The transmitter driver circuit of claim 5 , wherein:
the one or more tap delays comprises a variable tap delay having a variable delay duration; and
the one or more delayed signals comprises a delayed input signal having a variable delay relative to the digital input signal based on the variable delay duration of the variable tap delay.

8. The transmitter driver circuit of claim 7 , wherein the equalization driver varies the duration of the predefined period of time based on the variable delay of the delayed input signal.

9. The transmitter driver circuit of claim 1 , wherein:
the equalization driver provides equalization to the digital output signal based on a first data signal and a second data signal, the first data signal and the second data signal each having a disabling value and an enabling value;
the variable-resistance path switches between a baseline resistance in response to disabling values of the first and second signals and a low resistance in response to an enabling value of the first or second signal; and
the equalization driver further comprises a power source for:
providing positive polarity signal gain to the digital output signal via the variable-resistance path in response to an enabling value of the first signal; and
providing negative polarity signal gain to the digital output signal via the variable-resistance path in response to an enabling value of the second signal.

10. The transmitter driver circuit of claim 9 wherein the gain provided is voltage-mode gain.

11. A method for equalizing an output signal, comprising:
detecting an input data signal;
generating a delayed version of the input data signal; and
in response to detecting that a value of the input data signal has changed relative to the delayed version,
enabling a low-resistance path;
providing pre-emphasis to the output signal via the low-resistance path to increase the peak-to-peak amplitude of the output signal for a predetermined duration; and
at the end of the predetermined duration, disabling the low-resistance path and disabling pre-emphasis.

12. The method of claim 11 , wherein the pre-emphasis is voltage-mode pre-emphasis.

13. The method of claim 11 , wherein the duration is one unit interval of the input data signal.

14. The method of claim 11 , wherein the step of providing pre-emphasis comprises:
if the value of the input data signal has increased relative to the delayed version, providing positive-polarity pre-emphasis; and
if the value of the input data signal has decreased relative to the delayed version, providing negative-polarity pre-emphasis.

15. The method of claim 11 , wherein the step of generating a delayed version comprises introducing 1 unit interval of delay to the input data signal.

16. The method of claim 11 , wherein the step of generating a delayed version comprises introducing a variable amount of delay to the input data signal.

17. An equalization driver for providing equalization to an output signal based on a first data signal and a second data signal, the first data signal and the second data signal each having a disabling value and an enabling value, comprising:
a variable-resistance path for switching between a baseline resistance in response to disabling values of the first and second signals and a low resistance in response to an enabling value of the first or second signal; and
a power source for:
providing positive polarity signal gain to the output signal via the variable-resistance path in response to an enabling value of the first signal; and
providing negative polarity signal gain to the output signal via the variable-resistance path in response to an enabling value of the second signal.

18. The equalization driver of claim 17 wherein the gain provided is voltage-mode gain.

Assignees

• Chong Euhan
• Huawei Tech Co Ltd

Inventors

• Chong Euhan

Classifications

• H03K17/102

  in field-effect transistor switches · CPC title

• H04L25/03343

  Arrangements at the transmitter end · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L25/03885 Primary

  adaptive · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title