Apparatus and method for certificate enrollment

US10880100B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10880100-B2
Application numberUS-201816055732-A
CountryUS
Kind codeB2
Filing dateAug 6, 2018
Priority dateJul 14, 2016
Publication dateDec 29, 2020
Grant dateDec 29, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An apparatus includes a processor coupled to a memory wherein the processor and the memory are configured to provide a secure execution environment. The memory includes a shared secret value. The processor is configured to receive a certificate, wherein the certificate includes a device identifier and a digital signature. The processor validates the certificate based on the digital signature and the device identifier, recovers a cryptographic key based on the shared secret value and the device identifier, and performs a cryptographic operation based on the recovered cryptographic key.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus configured to operate in a secure execution environment, the apparatus comprising: a memory; and a processor coupled to the memory, wherein the memory is configured to store a shared secret value, wherein the processor is configured to: receive a certificate, wherein the certificate comprises a device identifier, a digital signature, and a plurality of diversifier values; validate the certificate based on the digital signature and the device identifier; recover a cryptographic key based on the shared secret value, the device identifier, and a diversifier value of the plurality of diversifier values; and perform a cryptographic operation based on the recovered cryptographic key, and wherein the plurality of diversifier values are public values. 2. The apparatus of claim 1 , wherein the certificate is validated further based on the diversifier value. 3. The apparatus of claim 1 , wherein the certificate comprises an encrypted private key, and the processor is further configured to decrypt the encrypted private key based on the recovered cryptographic key, and wherein the cryptographic operation is performed further based on the decrypted private key. 4. The apparatus of claim 3 , wherein the memory is further configured to store a hardware unique key, wherein the private key is decrypted further based on the hardware unique key, and wherein the cryptographic operation is performed further based on the decrypted private key. 5. The apparatus of claim 1 , wherein the processor is further configured to receive a public key corresponding to a certificate authority, wherein the certificate is validated further based on the public key, and wherein the public key is associated with a certificate authority, and the certificate is issued by the certificate authority. 6. The apparatus of claim 1 , wherein the processor is further configured to verify that the cryptographic operation is allowed by the certificate, and wherein the cryptographic operation is performed in response to the cryptographic operation being allowed. 7. The apparatus of claim 1 , wherein the recovered cryptographic key corresponds to one of a symmetric cryptographic key and an asymmetric cryptographic key. 8. The apparatus of claim 1 , wherein the recovered cryptographic key is based on one or more of a digital encryption standard and an advanced encryption standard. 9. The apparatus of claim 1 , wherein the recovered cryptographic key is an asymmetric cryptographic key based on one of a Rivest, Shamir, and Adleman cryptographic algorithm and an elliptic curve cryptography algorithm. 10. The apparatus of claim 9 , wherein the processor is further configured to generate an asymmetric key pair by: generating a plurality of pseudo random bytes by applying a one-way function to the shared secret value; and generating the asymmetric key pair by applying a deterministic process to the plurality of pseudo random bytes. 11. The apparatus of claim 1 , wherein the processor is further configured to generate an application specific key based on the diversifier value of the plurality of diversifier values. 12. The apparatus of claim 1 , wherein the processor is further configured to generate different application specific keys based on different diversifier values of the plurality of diversifier values. 13. The apparatus of claim 1 , wherein the diversifier value and the device identifier are configured to function as a public cryptographic salt. 14. A method for performing a cryptographic operation in a secure execution environment using a shared secret value, the method comprising: receiving a certificate, wherein the certificate comprises a device identifier, a plurality of diversifier values, and a digital signature; validating the certificate based on the device identifier and the digital signature; recovering a cryptographic key based on the shared secret value, the device identifier, and a diversifier value of the plurality of diversifier values; and performing a cryptographic operation based on the recovered cryptographic key, wherein the plurality of diversifier values are public values. 15. The method of claim 14 , wherein the certificate is validated further based on the diversifier value. 16. The method of claim 14 , further comprising generating an application specific key based on the diversifier value of the plurality of diversifier values. 17. The method of claim 14 , wherein the certificate comprises an encrypted private key, and the method further comprises decrypting the encrypted private key based on the recovered cryptographic key, and wherein the cryptographic operation is performed further based on the decrypted private key. 18. A non-transitory computer readable medium having a program code stored thereon that, when executed by a computer, causes the computer to perform a method for performing a cryptographic operation in a secure execution environment using a shared secret value, the method comprising: receiving a certificate, wherein the certificate comprises a device identifier, a plurality of diversifier values, and a digital signature; validating the certificate based on the device identifier and the digital signature; recovering a cryptographic key based on the shared secret value, the device identifier, and a diversifier value of the plurality of diversifier values; and performing a cryptographic operation based on the derived cryptographic key, wherein the plurality of diversifier values are public values. 19. The non-transitory computer readable medium of claim 18 , wherein the certificate is validated further based on the diversifier value. 20. The non-transitory computer readable medium of claim 18 , wherein the method further comprises generating an application specific key based on the diversifier value of the plurality of diversifier values. 21. The non-transitory computer readable medium of claim 18 , wherein the certificate comprises an encrypted private key, and the method further comprises decrypting the encrypted private key based on the recovered cryptographic key, and wherein the cryptographic operation is performed further based on the decrypted private key.

Assignees

Inventors

Classifications

  • Program or device authentication · CPC title

  • using key encryption key · CPC title

  • involving a third party or a trusted authority · CPC title

  • using asymmetric-key encryption or public key infrastructure [PKI], e.g. key signature or public key certificates · CPC title

  • based on the identity of the terminal or configuration, e.g. MAC address, hardware or software configuration or device fingerprint · CPC title

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What does patent US10880100B2 cover?
An apparatus includes a processor coupled to a memory wherein the processor and the memory are configured to provide a secure execution environment. The memory includes a shared secret value. The processor is configured to receive a certificate, wherein the certificate includes a device identifier and a digital signature. The processor validates the certificate based on the digital signature an…
Who is the assignee on this patent?
Huawei Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04L9/3268. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 29 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).