Selectively shielded connector channel

US10879651B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10879651-B2
Application numberUS-201716081541-A
CountryUS
Kind codeB2
Filing dateJun 16, 2017
Priority dateJun 18, 2016
Publication dateDec 29, 2020
Grant dateDec 29, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A connector system includes a wafer that has a shield that replaces standard ground terminals and an additional isolation shield to provide enhanced electrical isolation. To further improve electrical performance, transmit and receive channels can be provided in separate wafers on one side of connector system with a space or wafer between the transmit and signal wafers. On the other side of the connector system the wafer will have one or two spaces that are either black or filled with terminals that operate at lower frequencies. A conductive insert can provide further isolation intra-wafer.

First claim

Opening claim text (preview).

We claim: 1. A connector, comprising: a housing, a first wafer supported by the housing and having a first insulative frame and a first side and a second side and a first edge and a second edge, the first side having a first shield mounted thereon, the first shield having a plurality of channels extending from the first edge to the second edge, the first insulative frame supporting a plurality of pairs of signal terminals aligned in the plurality of channels, the first wafer having a first isolation shield mounted on the first side that is electrically connected to the first shield; a second wafer supported by the housing and having a second insulative frame and a third side and a fourth side and a first edge and a second edge, the third side facing the second side of the first wafer and having a second shield mounted thereon, the second shield having a plurality of channels extending from the first edge to the second edge, the second insulative frame supporting a plurality of pairs of signal terminals aligned in the plurality of channels, the second wafer having a second isolation shield mounted on the third side that is electrically connected to the second shield; and a single conductive insert mounted on the second side of the first wafer, the conductive insert extending between the first and second edge and being aligned with one of the plurality of channels and engaging the second isolation shield. 2. The connector of claim 1 , wherein the conductive insert has two side walls and a top wall and forms a U-shaped channel over one of the signal terminal pairs. 3. The connector of claim 2 , wherein the top wall has a plurality of projections that are configured to engage the second isolation shield. 4. The connector of claim 1 , wherein the first wafer has a top region with at least one signal pair, a bottom region with at least one signal pair and a central region positioned between the top and bottom regions, the central region having at least one signal pair, wherein the conductive insert is mounted in the central region. 5. The connector of claim 4 , wherein the channel aligned with the conductive insert does not include a terminal pair. 6. A connector, comprising: a housing; a first wafer supported by the housing, the first wafer having a first insulative frame and a first side and a second side and a first edge and a second edge, the first side having a first shield mounted thereon, the first shield having three channels extending from the first edge to the second edge, the first insulative frame supporting three pairs of signal terminals, each of the pairs of signal terminals arranged in one of the three channels, wherein the pairs of signal terminals and the channels are arranged in one of a top region, a bottom region and a central region, the central region being between the top and bottom region, the first wafer having a first isolation shield mounted on the first side that is electrically connected to the first shield; a second wafer supported by the housing, the second wafer having a second insulative frame and a third side and a fourth side and a first edge and a second edge, the third side facing the second side of the first wafer and having a second shield mounted thereon, the second shield having a plurality of channels extending from the first edge to the second edge, the second insulative frame supporting a plurality of pairs of signal terminals aligned in the plurality of channels, the second wafer having a second isolation shield mounted on the third side that is electrically connected to the second shield; and a single conductive insert mounted on the second side of the first wafer in, the conductive insert extending between the first and second edge and being aligned with the channel in the central region. 7. The connector of claim 6 , wherein the first shield has at least five channels and at least two channels of the at least five channels are in the top region and at least two channels of the at least five channels are in the bottom region. 8. The connector of claim 7 , wherein the first shield has more channels then there are pairs of signal terminals. 9. The connector of claim 8 , wherein the conductive insert is aligned with a channel that does not include a pair of signal terminal aligned therewith.

Assignees

Inventors

Classifications

  • Specific features or arrangements of connection of shield to conductive members · CPC title

  • for mounting on PCBs · CPC title

  • Shield structure · CPC title

  • using twisted pairs of wires · CPC title

  • Bases; Cases · CPC title

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Frequently asked questions

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What does patent US10879651B2 cover?
A connector system includes a wafer that has a shield that replaces standard ground terminals and an additional isolation shield to provide enhanced electrical isolation. To further improve electrical performance, transmit and receive channels can be provided in separate wafers on one side of connector system with a space or wafer between the transmit and signal wafers. On the other side of the…
Who is the assignee on this patent?
Molex Llc
What technology area does this patent fall under?
Primary CPC classification H01R13/6587. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 29 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).