Electronic device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10879461-B2
Application number	US-201916705070-A
Country	US
Kind code	B2
Filing date	Dec 5, 2019
Priority date	Sep 15, 2017
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.

First claim

What is claimed is:

1. An electronic device comprising a semiconductor memory,
wherein the semiconductor memory includes:
stack structures;
first capping layers disposed along sidewalls of the stack structures and covering first portions of the sidewalls of the stack structures;
second capping layers disposed along the sidewalls of the stack structures and covering the first capping layers and second portions of the sidewalls of the stack structures, the second portions being exposed by the first capping layers, wherein at least one of the first capping layers or the second capping layers include a hydrogen-based impurity; and
a gap fill layer filling one or more gaps between the stack structures,
wherein a concentration of the hydrogen-based impurity in the first capping layers is lower than a concentration of the hydrogen-based impurity in the second capping layers.

2. The electronic device of claim 1 , further comprising: third capping layers covering the second capping layers and third portions of the sidewalls of the stack structures, the third portions being exposed by the second capping layers, the third capping layers including the hydrogen-based impurity,
wherein the concentration of the hydrogen-based impurity in the second capping layers is lower than a concentration of the hydrogen-based impurity in the third capping layers.

3. The electronic device of claim 2 , wherein each of the stack structures includes a lower electrode, a switching material pattern, an intermediate electrode, a variable resistance pattern, and an upper electrode, which are sequentially stacked, and
wherein, for each of the stack structures, a corresponding first capping layer covers the upper electrode and a sidewall of the variable resistance pattern, a corresponding second capping layer covers the corresponding first capping layer and sidewalls of the intermediate electrode and the switching material pattern, and a corresponding third capping layer covers the corresponding second capping layer and a sidewall of the lower electrode.

4. The electronic device of claim 2 , wherein interfaces between the second capping layers and the third capping layers have been irradiated with ultraviolet light, plasma-treated, or both.

5. The electronic device of claim 2 , wherein an interface between the third capping layers and the gap fill layer has been irradiated with ultraviolet light, plasma-treated, or both.

6. The electronic device of claim 1 , wherein interfaces between the first capping layers and the second capping layers have been irradiated by ultraviolet light, plasma-treated, or both.

7. The electronic device of claim 1 , wherein the first capping layers include a nitride material.

8. The electronic device of claim 1 , wherein the hydrogen-based impurity includes H2, CH3, NH3, H2O, HF, HCl, or a combination thereof.

9. The electronic device of claim 1 , wherein each of the stack structures includes a switching material layer, an intermediate electrode layer, a variable resistance layer, and an upper electrode layer.

10. The electronic device of claim 9 , wherein the variable resistance layer includes a phase-change material.

11. An electronic device comprising a semiconductor memory,
wherein the semiconductor memory includes:
a stack structure including an electrode and a variable resistance pattern, wherein a sidewall of the stack structure includes a first portion, a second portion, and a third portion;
a first capping layer covering the first portion of the sidewall of the stack structure and exposing the second portion and the third portion;
a second capping layer covering the first capping layer and the second portion of the sidewall of the stack structure, wherein the second capping layer exposes the third portion; and
a third capping layer covering the second capping layer and the third portion,
wherein at least one of the first capping layer or the second capping layer includes a hydrogen-based impurity, and a concentration of the hydrogen-based impurity in the first capping layer is lower than a concentration of the hydrogen-based impurity in the second capping layer.

12. The electronic device of claim 11 , wherein the third capping layer includes the hydrogen-based impurity, and the concentration of the hydrogen-based impurity in the second capping layer is lower than a concentration of the hydrogen-based impurity in the third capping layer.

13. The electronic device of claim 11 , wherein the first capping layer includes a nitride material.

14. The electronic device of claim 11 , wherein the hydrogen-based impurity includes H2, CH3, NH3, H2O, HF, HCl, or a combination thereof.

15. The electronic device of claim 11 , wherein the variable resistance pattern includes a phase-change material.

16. The electronic device of claim 1 , wherein the sidewalls of the stack structures have a step shape.

17. The electronic device of claim 1 , wherein a width of each of the stack structures at each of the second portions is greater than a width of each of the stack structures at each of the first portions.

18. The electronic device of claim 1 , wherein each of the first capping layers includes a dehydrogenated nitride layer.

19. The electronic device of claim 11 , wherein the first capping layer, the second capping layer, and the third capping layer have different thicknesses.

20. The electronic device of claim 11 , wherein a thickness of the second capping layer is greater than a thickness of the first capping layer, and a thickness of the third capping layer is greater than the thickness of the second capping layer.

Assignees

• Sk Hynix Inc

Inventors

• Kim Hyo June
• Kim Chi Ho
• Cho Sang Hoon
• Hwang Eung Rim

Classifications

• H10N70/011 Primary

  Manufacture or treatment of multistable switching devices · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10N70/883

  Oxides or nitrides · CPC title

• H01L27/2481

  Electricity · mapped topic