Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same

Patent metadata

Field	Value
Publication number	US-10879457-B2
Application number	US-201916584731-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Mar 8, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

Semiconductor substrate adaptor configured to adapt a substrate of a first dimension to a second dimension, such that the substrate can be properly supported by a supporting mechanism (e.g., a wafer cassette) customized for substrates of the second dimension. The substrate adaptor may be made of quartz. The combination of the substrate adaptor and a substrate fitting therein causes no perturbation in various aspects of a semiconductor process. Therefore, the substrate adaptor conveniently enables a substrate of the first dimension to be processed in the same processing equipment and conditions as a substrate of the second dimension. A vertical substrate adaptor may have a semicircular body with a semicircular cutout for accommodating a wafer and can support a wafer vertically. A horizontal substrate adaptor may have a circular body with a circular cutout for accommodating an entire wafer and supporting the wafer horizontally.

First claim

What is claimed is:

1. A planar wafer adaptor comprising:
a planar body comprising a first boundary having a perimeter contour substantially equivalent to a portion of a semiconductor wafer of a first dimension;
one or more cutouts from the planar body; and
a slot disposed along a boundary of each of said one or more cutouts, wherein said slot is configured to receive an edge of a semiconductor wafer of a predefined dimension and to vertically accommodate said semiconductor wafer of said predefined dimension when said planar body is vertically oriented, wherein said planar body has a thermal mass that is substantially equivalent to a thermal mass of said semiconductor wafer of said first dimension minus a sum of thermal masses of one or more semiconductor wafers operable to be accommodated in said one or more cutouts at a same time.

2. The planar wafer adaptor of claim 1 , wherein said one or more cutouts comprise multiple cutouts, and wherein slots of said multiple cutouts are configured to accommodate semiconductor wafers of different predefined dimensions.

3. The planar wafer adaptor of claim 1 , wherein said one or more cutouts comprise multiple cutouts, and wherein slots of said multiple cutouts are configured to accommodate semiconductor wafers of a same predefined dimension.

4. The planar wafer adaptor of claim 1 , wherein a boundary of said slot has a perimeter contour substantially equivalent to a portion of said semiconductor wafer of said predefined dimension.

5. The planar wafer adaptor of claim 1 , wherein said planar body comprises quartz.

6. The planar wafer adaptor of claim 4 , wherein said first boundary of said planar body comprises a notch for orientation thereof.

7. The planar wafer adaptor of claim 6 , wherein said first boundary of said planar body is configured to fit in a cassette configured to accommodate a plurality of semiconductor wafers of said first dimension.

8. The planar wafer adaptor of claim 1 , wherein said first boundary substantially defines one of: a semicircle; and an arc less than a semicircle.

9. The planar wafer adaptor of claim 1 , wherein said one or more cutouts define one or more semicircles or minor segments of one or more circles.

10. The planar wafer adaptor of claim 1 , wherein said slot is 3 mm in depth.

11. A planar wafer adaptor comprising:
a planar body comprising a first boundary having a perimeter contour substantially equivalent to a portion of a semiconductor wafer of a first dimension; and
one or more cutouts from the planar body in a form of one or more through holes on said planar body, wherein each cutout comprises:
a boundary having a perimeter contour substantially equivalent to a semiconductor wafer of a predefined dimension; and
a lateral step disposed along said boundary and configured to support an edge of said semiconductor wafer of said predefined dimension and configured to align said semiconductor wafer of said predefined dimension in a horizontal orientation when said planar body is aligned horizontally,
wherein said planar body has a thermal mass that is substantially equal to a thermal mass of a semiconductor wafer of said first dimension minus a sum of thermal masses of one or more semiconductor wafers operable to be accommodated in all of said one or more cutouts.

12. The planar wafer adaptor of claim 11 , wherein said planar body comprises quartz.

13. The planar wafer adaptor of claim 11 , wherein said first boundary comprises a notch for orientation thereof.

14. The planar wafer adaptor of claim 11 , wherein said first boundary is configured to fit in a cassette configured to accommodate a plurality of semiconductor wafers of said first dimension.

15. The planar wafer adaptor of claim 11 , wherein said first boundary substantially defines a circle.

16. The planar wafer adaptor of claim 11 , wherein said one or more cutouts define substantially one or more circles.

17. The planar wafer adaptor of claim 11 , wherein said boundary comprises a flat cut.

18. The planar wafer adaptor of claim 11 , wherein a semiconductor wafer of said first dimension is 300 mm in diameter.

19. The planar wafer adaptor of claim 11 , wherein said semiconductor wafer of said predefined dimension is one of: 50 mm; 100 mm; 150 mm; and 200 mm in diameter.

20. The planar wafer adaptor of claim 11 , wherein said one or more cutouts comprise multiple cutouts, and wherein lateral steps of said multiple cutouts are configured to accommodate semiconductor wafers of different predefined dimensions or of a same predefined dimension.

Assignees

• Spin Memory Inc

Inventors

• Vasquez Jorge
• Yam Danny

Classifications

• H10P72/7621

  characterised by supporting two or more semiconductor substrates · CPC title

• H10P72/13

  Horizontal boat type carrier whereby the substrates are vertically supported, e.g. comprising rod-shaped elements · CPC title

• H10P72/127

  characterised by the substrate support · CPC title

• H10P72/0436 Primary

  mainly by radiation · CPC title

• H01L43/08

  Electricity · mapped topic