Device integrated with junction field effect transistor and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10879385-B2
Application number	US-201716329413-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Aug 31, 2016
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain (201) having a first conduction type; and a first conduction type region (214) disposed on a front face of the drain; the JFET region further includes: a JFET source (208) having a first conduction type; a first well (202) having a second conduction type; a metal electrode (212) formed on the JFET source (208), which is in contact with the JFET source (208); a JFET metal gate (213) disposed on the first well (202) at both sides of the JFET source (208); and a first clamping region (210) located below the JFET metal gate (213) and within the first well (202).

First claim

What is claimed is:

1. A method for manufacturing a device integrated with a Junction Field-Effect Transistor (JFET), the device comprising a JFET region and a power device region, the method comprising:
providing a substrate of a first conduction type on which a first conduction type region is formed; while the first conduction type is opposite to a second conduction type;
implanting ions of the second conduction type into the first conduction type region and forming a first well within the first conduction type region by driving-in;
growing a field oxide layer and a gate oxide layer on a surface of the first conduction type region in sequence, forming a polysilicon layer on the surface of the first conduction type region, and implanting ions of the second conduction type into the first conduction type region of the power device region and forming a plurality of second wells by driving-in;
implanting ions of the first conduction type into the second well of the power device region to form a power device source;
implanting ions of the first conduction type between two adjacent second wells of the JFET region to form a JFET source;
photoetching and etching a contact hole, implanting ions of the second conduction type into the contact hole, to form a clamping region within the first well and at a bottom of the second well, wherein an ion concentration of the clamping region is greater than that of the first well; and
depositing a metal layer and filling the contact hole with the metal layer to form a metal electrode of the JFET source, a JFET metal gate and a metal contact of the power device source respectively.

2. The method according to claim 1 , wherein a step of forming an isolation well within the first conduction type region comprises: forming the isolation well at the boundary between the JFET region and the power device region, as isolation of the JFET region and the power device region.

3. The method according to claim 1 , wherein in the step of implanting ions of the second conduction type into the first conduction type region and forming the plurality of second wells by driving-in, the implanting is carried out by serving the field oxide layer and the polysilicon layer as a mask.

4. The method according to claim 3 , wherein between the step of forming the power device source and the step of forming the JFET source, further comprises a step of
forming an implantation barrier layer which is also superposed onto surfaces of the field oxide layer and the polysilicon layer; and
implanting ions of the second conduction type into the second well of the power device region to form an unclamped inductive switching region below the power device source within the second well, while an implantation energy is greater than that of the step of implanting ions of the first conduction type into the second well of the power device region, and the field oxide layer and the polysilicon layer superposed with the implantation barrier layer blocking the implanted ions of the second conduction type.

5. The method according to claim 1 , wherein prior to the step of photoetching and etching the contact hole, further comprises:
etching a trench in each of the first wells and each of the second wells, wherein the JFET metal gate is formed by a metal layer filled in the trench in the first well, and the metal contact of the power device source is formed by a metal layer filled in the trench in the second well.

6. The method according to claim 5 , wherein after the step of etching the trench in each of the second wells, further comprises: implanting ions of the second conduction type into the trench, forming an ohmic contact region of the second conduction type at a place in contact with a bottom of the trench within each of the second wells and, and at a place in contact with a bottom of the trench within each of the first wells.

7. The method according to claim 6 , wherein further comprises a step of re-implanting ions of the second conduction type, to form a clamping region of the second conduction type at a bottom of the second well and within the first well at both sides of the JFET source.

8. The method according to claim 7 , wherein an implantation energy in the step of re-implanting ions of the second conduction type is 480 keV.

9. The method according to claim 1 , wherein the first conduction type is an N type, the second conduction type is a P type, and the first conduction type region is an N type epitaxial layer.

10. The method according to claim 1 , wherein the device is a Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor (VDMOS).

11. The method according to claim 1 , wherein in the step of implanting ions of the second conduction type into the first conduction type region and driving-in, an implantation concentration is from 1.5E13 cm −2 to 2.2E13 cm −2 ;
in the step of forming the first well in the first conduction type region, a well depth of the formed first well is from 8.5 micrometers to 13.5 micrometers.

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Gu Yan
• Cheng Shikang
• Zhang Sen

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D89/00

  Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00 · CPC title

• H10D84/87

  of PN-junction gate FETs · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title