Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-10879376-B2
Application number	US-201916353001-A
Country	US
Kind code	B2
Filing date	Mar 14, 2019
Priority date	Mar 27, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

To form p-type semiconductor regions in a gallium nitride (GaN)-based semiconductor by ion implantation. A method for manufacturing a semiconductor device comprises forming first grooves, depositing, and ion-implanting. At the step of forming the first grooves, the first grooves are formed in a stacked body including a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first grooves each have a bottom portion located in the first semiconductor layer. At the depositing step, the p-type impurity is deposited on side portions and the bottom portions of the first grooves. At the ion-implanting step, the p-type impurity is ion-implanted into the first semiconductor layer through the first grooves.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
forming first grooves in a stacked body including a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity, the first grooves each having a bottom portion located in the first semiconductor layer;
depositing the p-type impurity on side portions and the bottom portions of the first grooves by non-epitaxially-formed adhesion of the p-type impurity onto the side portions and the bottom portions of the first grooves to form a p-type impurity deposition region in each of the first grooves after the forming of the first grooves, wherein in the depositing step, delta-doping is performed to deposit the p-type impurity on the side portions and the bottom portions of the first grooves; and
ion-implanting the p-type impurity through the p-type impurity deposition region of the first grooves and into the first semiconductor layer to form a p-type semiconductor region underneath the p-type impurity deposition region on the bottom portions of the first grooves after the depositing of the p-type impurity on side portions and bottom portions of the first grooves.

2. The method for manufacturing the semiconductor device according to claim 1 , further comprising growing a gallium nitride (GaN)-based semiconductor layer containing the p-type impurity on the first grooves after the depositing step.

3. The method for manufacturing the semiconductor device according to claim 1 ,
wherein in the step of forming the first grooves, a mask in which regions where the first grooves are formed are opened is used to form the first grooves, and
wherein in the ion-implanting step, the mask is used to perform the ion implantation.

4. The method for manufacturing the semiconductor device according to claim 1 , further comprising forming first electrodes in the first grooves after the depositing step and the ion-implanting step are performed.

5. The method for manufacturing the semiconductor device according to claim 1 , further comprising:
forming a second groove in the stacked body, the second groove penetrating the second semiconductor layer and having a bottom portion located in the first semiconductor layer; and
forming a second electrode in the second groove, the second electrode including a gate electrode.

6. The method for manufacturing the semiconductor device according to claim 5 ,
wherein in the step of forming the second groove, the first grooves or structures stacked in the first grooves are used as alignment marks to form the second groove.

Assignees

• Toyoda Gosei Kk

Inventors

• Niwa Takaki
• Fujii Takahiro
• Kosaki Masayoshi

Classifications

• H10P95/904

  of Group III-V semiconductors · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/646

  of Group III-V materials · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/206

  into Group III-V semiconductors · CPC title