Method for manufacturing semiconductor structure

Patent metadata

Field	Value
Publication number	US-10879361-B2
Application number	US-201916521495-A
Country	US
Kind code	B2
Filing date	Jul 24, 2019
Priority date	Jun 22, 2017
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A method for manufacturing a semiconductor structure including following steps is provided. A dielectric layer is formed on a substrate. A polysilicon layer is formed on the dielectric layer. Ion implantation processes are performed to the polysilicon layer by using a fluorine dopant. Implantation depths of the ion implantation processes are different. A fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth. After the ion implantation processes, a thermal process is performed to the polysilicon layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
forming a dielectric layer on a substrate;
forming a polysilicon layer on the dielectric layer;
performing ion implantation processes to the polysilicon layer by using a fluorine dopant, wherein implantation depths of the ion implantation processes are different, a fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth, and a fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer, and fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer; and
performing a thermal process to the polysilicon layer after the ion implantation processes.

2. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein a method of forming the dielectric layer comprises thermal oxidation or chemical vapor deposition.

3. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein a method of forming the polysilicon layer comprises chemical vapor deposition.

4. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein the polysilicon layer comprises an unpatterned polysilicon layer or a patterned polysilicon layer.

5. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein the step of performing ion implantation processes to the polysilicon layer is performed before a lightly doped drain, a source region or a drain region is formed.

6. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein the fluorine dopant peak concentrations comprise:
a first fluorine dopant peak concentration, close to the bottom portion of the polysilicon layer; and
a second fluorine dopant peak concentration, close to the top portion of the polysilicon layer.

7. The method for manufacturing the semiconductor structure as claimed in claim 6 , wherein the fluorine dopant peak concentrations further comprise:
a third fluorine dopant peak concentration, wherein compared to the second fluorine dopant peak concentration, the third fluorine dopant peak concentration is closer to the top portion of the polysilicon layer.

8. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein after the thermal process, the fluorine dopant concentration in the polysilicon layer still presents the Gaussian distributions.

9. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein implantation energy of the ion implantation process with the deeper implantation depth is greater than implantation energy of the ion implantation process with the shallower implantation depth.

10. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein the ion implantation processes comprise:
performing a first ion implantation process and a second ion implantation process to the polysilicon layer,
wherein a first fluorine dopant concentration of the first ion implantation process is smaller than a second fluorine dopant concentration of the second ion implantation process, and
first implantation energy of the first ion implantation process is greater than second implantation energy of the second ion implantation process.

11. The method for manufacturing the semiconductor structure as claimed in claim 10 , wherein the ion implantation processes further comprise:
performing a third ion implantation process to the polysilicon layer,
wherein the second fluorine dopant concentration of the second ion implantation process is smaller than a third fluorine dopant concentration of the third ion implantation process, and
the second implantation energy of the second ion implantation process is greater than third implantation energy of the third ion implantation process.

12. The method for manufacturing the semiconductor structure as claimed in claim 11 , wherein the first ion implantation process, the second implantation process and the third ion implantation process are sequentially performed.

13. The method for manufacturing the semiconductor structure as claimed in claim 11 , wherein the first ion implantation process, the second implantation process and the third ion implantation process are not sequentially performed.

14. A method for manufacturing a semiconductor structure, comprising:
forming a dielectric layer on a substrate;
forming a polysilicon layer on the dielectric layer;
performing ion implantation processes to the polysilicon layer by using a fluorine dopant, wherein implantation depths of the ion implantation processes are different, a fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth, and implantation energy of the ion implantation process with the deeper implantation depth is greater than implantation energy of the ion implantation process with the shallower implantation depth; and
performing a thermal process to the polysilicon layer after the ion implantation processes.

15. A method for manufacturing a semiconductor structure, comprising:
forming a dielectric layer on a substrate;
forming a polysilicon layer on the dielectric layer;
performing ion implantation processes to the polysilicon layer by using a fluorine dopant, wherein implantation depths of the ion implantation processes are different, a fluorine dopant concentration of the ion implantation process with a deeper implantation depth is smaller than a fluorine dopant concentration of the ion implantation process with a shallower implantation depth, and the ion implantation processes comprise:
performing a first ion implantation process and a second ion implantation process to the polysilicon layer,
wherein a first fluorine dopant concentration of the first ion implantation process is smaller than a second fluorine dopant concentration of the second ion implantation process, and
first implantation energy of the first ion implantation process is greater than second implantation energy of the second ion implantation process; and

performing a thermal process to the polysilicon layer after the ion implantation processes.

Assignees

• United Microelectronics Corp

Inventors

• Pan Chen-Wei

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/209

  in silicon to make buried insulating layers · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D64/01306 Primary

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title