Display panel having pad disposed on bottom surface of substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10879339-B2
Application number	US-201916538783-A
Country	US
Kind code	B2
Filing date	Aug 12, 2019
Priority date	Oct 22, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A display panel including a first array substrate, a first pad, and a second pad is provided. The first array substrate includes a first substrate, a first active element, a first display element, and a second display element. The first substrate has a top surface and a bottom surface disposed opposite to each other. The first active element is disposed on the top surface of the first substrate. The first display element is disposed on the top surface of the first substrate and is electrically connected to the first active element. The second display element is disposed on the top surface of the first substrate and is disposed separately from the first display element. The first pad and the second pad are disposed on the bottom surface of the first substrate, wherein the first active element is electrically connected to the first pad, each of the first pad and the second pad includes an embedded part and a protruded part, the embedded part is located in the first substrate, and the protruded part is protruded from the bottom surface of the first substrate.

First claim

What is claimed is:

1. A display panel, comprising:
a first array substrate, comprising:
a first substrate having a top surface and a bottom surface disposed opposite to each other;
a first active element disposed on the top surface of the first substrate;
a first display element disposed on the top surface of the first substrate and electrically connected to the first active element; and
a second display element disposed on the top surface of the first substrate and disposed separately from the first display element; and

a first pad and a second pad disposed on the bottom surface of the first substrate, wherein the first active element is electrically connected to the first pad, each of the first pad and the second pad comprises an embedded part and a protruded part, the embedded part is located in the first substrate, and the protruded part is protruded from the bottom surface of the first substrate, wherein a vertical projection of an edge of the embedded part of the first pad on the first substrate is 1 micron to 1000 microns apart from a vertical projection of an edge of the protruded part of the first pad on the first substrate, and a vertical projection of an edge of the embedded part of the second pad on the first substrate is 1 micron to 1000 microns from a vertical projection of an edge of the protruded part of the second pad on the first substrate.

2. The display panel of claim 1 , wherein the first array substrate further comprises:
a second active element disposed on the top surface of the first substrate and disposed separately from the first active element and electrically connected to the second display element and the second pad.

3. The display panel of claim 2 , further comprising a circuit layer electrically connected to the first array substrate via an anisotropic conductive layer, the first pad and the second pad, wherein the anisotropic conductive layer is between the first array substrate and the circuit layer.

4. The display panel of claim 3 , wherein the first array substrate further comprises a signal line disposed on the top surface of the first substrate and electrically connected between the first active element and the first pad, and the circuit layer comprises a gate driving circuit.

5. The display panel of claim 1 , further comprising:
a first anisotropic conductive layer disposed on the bottom surface of the first substrate;
a second array substrate, comprising:
a second substrate; and
a second active element disposed on the second substrate, wherein the first anisotropic conductive layer is between the first array substrate and the second array substrate, and the second active element is electrically connected to the second display element of the first array substrate via the first anisotropic conductive layer and the second pad; and

a plurality of third pads disposed on a bottom surface of the second substrate, wherein each of the third pads comprises a embedded part and a protruded part, the embedded part of the third pad is located in the second substrate, and the protruded part of the third pad is protruded from the bottom surface of the second substrate.

6. The display panel of claim 5 , further comprising a circuit layer electrically connected to the second array substrate via a second anisotropic conductive layer and the third pads, wherein the second anisotropic conductive layer is between the second array substrate and the circuit layer.

7. The display panel of claim 6 , wherein the second array substrate further comprises a signal line disposed on a top surface of the second substrate and electrically connected between the second active element and one of the third pads, and the circuit layer comprises a gate driving circuit.

8. The display panel of claim 5 , further comprising an electronic element electrically connected to the second array substrate via a second anisotropic conductive layer and the third pads, wherein the second anisotropic conductive layer is between the second array substrate and the electronic element.

9. The display panel of claim 1 , further comprising an electronic element electrically connected to the first array substrate via an anisotropic conductive layer, the first pad and the second pad, wherein the anisotropic conductive layer is between the first array substrate and the electronic element.

10. The display panel of claim 1 , wherein the embedded part and the protruded part belong to a same film layer.

11. The display panel of claim 1 , wherein a protruding height of the protruded part is substantially equal to a thickness of the embedded part.

12. The display panel of claim 1 , wherein the first array substrate further comprises:
a connecting structure located in the first substrate and electrically connected to the first pad and the first active element.

Assignees

• Au Optronics Corp

Inventors

• Ke Tsung-Ying
• Chen Yung-Chih
• Hwu Keh-Long
• Wang Wan-Tsang
• Liu Chun-Hsin

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0212 Primary

  comprising manufacture, treatment or coating of substrates · CPC title

• H01L27/3276 Primary

  Electricity · mapped topic