Stacked sensor with integrated capacitors

Patent metadata

Field	Value
Publication number	US-10879291-B2
Application number	US-201816201633-A
Country	US
Kind code	B2
Filing date	Nov 27, 2018
Priority date	Nov 27, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A three-dimensional (3D) stack is provided and includes a capacitor layer and an integrated circuit (IC) layer. The capacitor layer includes capacitors and capacitor layer connectors respectively communicative with corresponding capacitors. The IC layer is stacked vertically with the capacitor layer and is hybridized to a detector. The IC layer includes IC layer connectors respectively communicative with corresponding capacitor layer connectors.

First claim

What is claimed is:

1. A three-dimensional (3D) stack, comprising:
a detector layer comprising a detector array having a detector footprint;
a capacitor layer comprising capacitors encompassed within the detector footprint and capacitor layer connectors respectively communicative with corresponding capacitors; and
an integrated circuit (IC) layer stacked vertically with the detector layer above the IC layer and the capacitor layer below the IC layer, the IC layer being hybridized to the detector layer,
wherein:
the IC layer comprises IC layer connectors respectively communicative with corresponding capacitor layer connectors, and
corresponding ones of the capacitor layer connectors, the capacitors and the IC layer connectors are aligned vertically.

2. The 3D stack according to claim 1 , wherein the capacitor layer and the IC layer respectively comprise coplanar sidewalls.

3. The 3D stack according to claim 1 , wherein:
the capacitor layer comprises a support structure comprising dielectric material in which the capacitors are suspended, and
an uppermost surface of each of the capacitors is coplanar with an uppermost surface of the dielectric material of the support structure of the capacitor layer.

4. The 3D stack according to claim 1 , wherein each of the capacitors has substantially a same size and shape as all other capacitors in the capacitor layer.

5. The 3D stack according to claim 1 , wherein the IC layer comprises:
a dielectric layer;
a read-out IC (ROIC) extending along a lower surface of the IC layer; and
contact vias extending from an upper surface of the ROIC and through the dielectric layer to be respectively communicative with the IC layer connectors and encompassed within the detector footprint.

6. The 3D stack according to claim 5 , wherein:
the capacitor layer connectors are respectively communicative with and partially misaligned relative to corresponding capacitors and the IC layer connectors are respectively communicative with and partially misaligned relative to corresponding capacitor layer connectors, and
the corresponding ones of the capacitor layer connectors, the capacitors and the IC layer connectors are aligned vertically with the corresponding ones of the contact vias.

7. The 3D stack according to claim 1 , further comprising one or more adhesives vertically interposed between the IC layer and the capacitor layer.

8. A three-dimensional (3D) stack, comprising:
a detector layer comprising a first upper surface receptive of electro-magnetic (EM) signals, a first lower surface, first connectors arrayed along the first lower surface and a detector array having a detector footprint;
a capacitor layer comprising a support structure comprising dielectric material having a second upper surface, capacitors suspended within the dielectric material of the support structure of the capacitor layer and encompassed within the detector footprint and second connectors respectively communicative with corresponding capacitors and arrayed along the second upper surface; and
an integrated circuit (IC) layer hybridized to the detector layer and comprising a third upper surface, a second lower surface, third connectors respectively communicative with corresponding first connectors and arrayed along the third upper surface and fourth connectors respectively communicative with corresponding second connectors and arrayed along the second lower surface,
wherein:
the detector layer, the capacitor layer and the IC layer are stacked vertically with the detector layer above the IC layer and the capacitor layer below the IC layer, and
corresponding ones of the capacitors and the first connectors, the second connectors, the third connectors and the fourth connectors are aligned vertically.

9. The 3D stack according to claim 8 , wherein the detector layer, the capacitor layer and the IC layer respectively comprise coplanar sidewalls.

10. The 3D stack according to claim 8 , wherein:
an uppermost surface of each of the capacitors is coplanar with the second upper surface of the dielectric material of the support structure of the capacitor layer, and
each of the capacitors has substantially a same size and shape as all the other capacitors in the capacitor layer.

11. The 3D stack according to claim 8 , wherein the IC layer comprises:
a dielectric layer;
a read-out IC (ROIC) extending along the second lower surface; and
contact vias extending from an upper surface of the ROIC and through the dielectric layer to be respectively communicative with corresponding third and fourth connectors and encompassed within the detector footprint.

12. The 3D stack according to claim 11 , wherein:
the second connectors are respectively communicative with and partially misaligned relative to corresponding capacitors, the third connectors are respectively communicative with and partially misaligned relative to corresponding first connectors and the fourth connectors are respectively communicative with and partially misaligned relative to corresponding second connectors, and
the corresponding ones of the capacitors and the first connectors, the second connectors, the third connectors and the fourth connectors are aligned vertically with the corresponding ones of the contact vias.

13. The 3D stack according to claim 8 , further comprising one or more adhesives vertically interposed between the detector layer and the IC layer and between the IC layer and the capacitor layer.

14. A three-dimensionally (3D) stacked focal plane array (FPA) module, comprising:
a detector layer comprising a detector array having a detector footprint;
a capacitor layer comprising capacitors encompassed within the detector footprint; and
an integrated circuit (IC) layer comprising a read-out integrated circuit (ROIC) and contact vias extending upwardly from the ROIC, the IC layer being stacked vertically between the capacitor layer and the detector layer with the detector layer above the IC layer and the capacitor layer below the IC layer,
each of the detector layer and the IC layer being hybridized to one another to enable communication between the detector array and the IC layer, and
each of the capacitor layer and the IC layer being hybridized to one another to enable communication between the capacitors and the IC layer,
wherein:
the 3D stacked FPA module further comprises first sets of connectors by which the contact vias are respectively communicative with the detector array and second sets of connectors by which the capacitors are respectively communicative with the ROIC, and
corresponding ones of the first connectors, the contact vias, the second connectors and the capacitors are aligned vertically.

15. The 3D stacked FPA module according to claim 14 , wherein the detector layer, the capacitor layer and the IC layer respectively comprise coplanar sidewalls.

16. The 3D stacked FPA module according to claim 14 , wherein:
wherein the capacitor layer comprises a support structure comprising dielectric material in which the capacitors are suspended,
an uppermost surface of each of the capacitors is coplanar with an uppermost surface of the dielectric material of the support structure of the capacitor layer, and
each of the capacitors has substantially a same size and shape as all the other capacitors in the capacitor layer.

17. The 3D stacked FPA module according to claim 14 , wherein the IC layer comprises:
a dielectric layer;
the read-out IC (ROIC), which extends along a lower surface of the IC layer; and
the contact vias, which extend upwardly from the ROIC and throu

Assignees

• Raytheon Co

Inventors

• Malone Neil R
• Kilcoyne Sean P
• Harris Micky

Classifications

• H10F39/811

  Interconnections · CPC title

• H10F39/018

  of hybrid image sensors · CPC title

• H10F39/809 Primary

  of hybrid image sensors · CPC title

• H01L27/1469

  Electricity · mapped topic

• H01L27/14634 Primary

  Electricity · mapped topic