Memory device including common mode extractor

Patent metadata

Field	Value
Publication number	US-10878869-B2
Application number	US-201816192975-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Nov 17, 2017
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A memory device may be configured to receive a differential data strobe signal and an external data signal from outside the memory device, the memory device may include control circuitry configured to, extract a common mode of the differential data strobe signal to generate a common mode signal, generate an internal data signal based on the external data signal and the common mode signal, and generate an internal data strobe signal based on the differential data strobe signal, the internal data strobe signal associated with latching the internal data signal.

First claim

What is claimed is:

1. A memory device configured to receive a differential data strobe signal and an external data signal from outside the memory device, the memory device comprising:
control circuitry configured to,
extract a common mode of the differential data strobe signal to generate a common mode signal such that a voltage level of the common mode signal is between a logic-high voltage level and a logic-low voltage level of the external data signal,
compare a voltage level of the external data signal and the voltage level of the common mode signal,
generate an internal data signal based on a result of comparing the voltage level of the external data signal and the voltage level of the common mode signal, and
generate an internal data strobe signal based on the differential data strobe signal, the internal data strobe signal associated with latching the internal data signal.

2. The memory device of claim 1 , wherein
the logic-high voltage level of the external data signal is a same as a logic-high voltage level of the differential data strobe signal, and
the logic-low voltage level of the external data signal is the same as a logic-high voltage level of the differential data strobe signal.

3. The memory device of claim 1 , wherein the control circuitry is further configured to generate a reference voltage signal such that the reference voltage signal has a voltage level between a logic-high voltage level and a logic-low voltage level of the external data signal.

4. The memory device of claim 3 , wherein the control circuitry is further configured to,
select one of the reference voltage signal and the common mode signal to generate a selected one of the reference voltage signal and the common mode signal; and
generate the internal data signal based on the selected one of the reference voltage signal and the common mode signal.

5. The memory device of claim 4 , wherein the control circuitry is further configured to generate the internal data signal based on the reference voltage signal and the selected one of the reference voltage signal and the common mode signal.

6. The memory device of claim 4 , wherein the control circuitry is further configured to,
compare a voltage level of the reference voltage signal with a voltage level of a first determination voltage to generate a first comparison result, and
compare the voltage level of the reference voltage signal with a voltage level of a second determination voltage to generate a second comparison result.

7. The memory device of claim 6 , wherein the control circuitry is further configured to,
select one of the reference voltage signal and the common mode signal based on the first comparison result and the second comparison result.

8. The memory device of claim 6 , wherein the control circuitry is configured to generate the common mode signal in response to one or more of the first comparison result and the second comparison result.

9. A memory device configured to receive a differential clock signal and an external command/address signal from outside the memory device, the memory device comprising:
control circuitry configured to,
extract a common mode of the differential clock signal to generate a clock common mode signal such that a voltage level of the clock common mode signal is between a logic-high voltage level and a logic-low voltage level of the external command/address signal,
compare a voltage level of the external command/address signal and the voltage level of the clock common mode signal,
generate an internal command/address signal based on a result of comparing the voltage level of the external command/address signal and the voltage level of the clock common mode signal, and
generate an internal clock signal based on the differential clock signal, the internal clock signal being associated with latching the internal command/address signal.

10. The memory device of claim 9 , wherein
the logic-high voltage level of the external command/address signal is a same as a logic-high voltage level of the differential clock signal, and
the logic-low voltage level of the external command/address signal is the same as a logic-low voltage level of the differential clock signal.

11. The memory device of claim 9 , wherein the control circuitry is further configured to,
generate a reference voltage signal having a voltage level between a logic-high voltage level and a logic-low voltage level of the external command/address signal, and
generate the internal command/address signal based on one of the reference voltage signal and the clock common mode signal.

12. The memory device of claim 11 , wherein the control circuitry is further configured to,
compare a voltage level of the reference voltage signal with a voltage level of a first determination voltage to generate a first comparison result, and
compare the voltage level of the reference voltage signal with a voltage level of a second determination voltage to generate a second comparison result.

13. The memory device of claim 12 , wherein the control circuitry is configured to generate the clock common mode signal based on one or more of the first comparison result and the second comparison result.

14. A memory device configured to receive a differential data strobe signal and an external data signal from a memory controller, the memory device comprising:
control circuitry configured to,
extract a common mode of the differential data strobe signal to generate a common mode signal such that a voltage level of the common mode signal is same as an average of a logic-high voltage level and a logic-low voltage level of the external data signal, and
generate an internal data signal based on the external data signal and the common mode signal.

15. The memory device of claim 14 , wherein the control circuitry is further configured to generate a reference voltage signal such that the reference voltage signal has a voltage level between the logic-high voltage level and the logic-low voltage level of the external data signal.

16. The memory device of claim 15 , wherein the control circuitry is further configured to,
select, in response to a selection signal, one of the reference voltage signal and the common mode signal to generate a selected one of the reference voltage signal and the common mode signal, and
generate the internal data signal based on the selected one of the reference voltage signal and the common mode signal.

17. The memory device of claim 16 , wherein the control circuitry is configured to receive the selection signal from the memory controller.

18. The memory device of claim 16 , wherein the control circuitry is further configured to,
compare a voltage level of the reference voltage signal with the voltage level of a first determination voltage to generate a first comparison result,
compare the voltage level of the reference voltage signal with a voltage level of a second determination voltage to generate a second comparison result, and
generate the selection signal based on one or more of the first comparison result and the second comparison result.

19. The memory device of claim 18 , wherein the control circuitry is configured to generate the internal data signal and the selection signal based on a same control signal from the memory controller.

20. The memory device of claim 18 , wherein the control circuitry is configured to generate the common mode signal based on the selection signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Ju-Ho
• Jung Han-Gi
• Choi Hun-Dae

Classifications

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C8/18 Primary

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G06F3/0613

  in relation to throughput · CPC title